R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 14

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.4
6.5
6.6
6.7
6.8
Section 7 User Break Controller (UBC)............................................................ 143
7.1
7.2
7.3
7.4
7.5
Section 8 Bus Controller (BSC) ........................................................................ 155
8.1
8.2
Rev. 2.00 Sep. 16, 2009 Page xii of xxviii
Interrupt Sources............................................................................................................... 120
6.4.1
6.4.2
Interrupt Exception Handling Vector Table...................................................................... 122
Interrupt Control Modes and Interrupt Operation............................................................. 127
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
CPU Priority Control Function Over DTC and DMAC.................................................... 136
Usage Notes ...................................................................................................................... 139
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
Features............................................................................................................................. 143
Block Diagram.................................................................................................................. 144
Register Descriptions........................................................................................................ 145
7.3.1
7.3.2
7.3.3
Operation .......................................................................................................................... 150
7.4.1
7.4.2
7.4.3
Usage Notes ...................................................................................................................... 152
Features............................................................................................................................. 155
Register Descriptions........................................................................................................ 158
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
External Interrupts ............................................................................................ 120
Internal Interrupts ............................................................................................. 121
Interrupt Control Mode 0.................................................................................. 127
Interrupt Control Mode 2.................................................................................. 129
Interrupt Exception Handling Sequence ........................................................... 131
Interrupt Response Times ................................................................................. 132
DTC and DMAC Activation by Interrupt ......................................................... 133
Conflict between Interrupt Generation and Disabling ...................................... 139
Instructions that Disable Interrupts................................................................... 140
Times when Interrupts are Disabled ................................................................. 140
Interrupts during Execution of EEPMOV Instruction ...................................... 140
Interrupts during Execution of MOVMD and MOVSD Instructions................ 140
Interrupts of Peripheral Modules ...................................................................... 141
Break Address Register n (BARA, BARB, BARC, BARD) ............................ 146
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 147
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 148
Setting of Break Control Conditions................................................................. 150
PC Break........................................................................................................... 150
Condition Match Flag ....................................................................................... 151
Bus Width Control Register (ABWCR)............................................................ 159
Access State Control Register (ASTCR) .......................................................... 160
Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 161
Read Strobe Timing Control Register (RDNCR) ............................................. 166
CS Assertion Period Control Registers (CSACR) ............................................ 167