R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 17

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
9.4
9.5
9.6
9.7
9.8
9.9
Section 10 Data Transfer Controller (DTC) ......................................................339
10.1
10.2
10.3
10.4
9.3.7
9.3.8
Transfer Modes ................................................................................................................. 285
Operations......................................................................................................................... 286
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10
9.5.11
DMA Transfer End ........................................................................................................... 328
Relationship among DMAC and Other Bus Masters ........................................................ 331
9.7.1
9.7.2
Interrupt Sources............................................................................................................... 333
Usage Notes ...................................................................................................................... 336
9.9.1
9.9.2
9.9.3
9.9.4
Features............................................................................................................................. 339
Register Descriptions........................................................................................................ 341
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
Activation Sources............................................................................................................ 349
Location of Transfer Information and DTC Vector Table ................................................ 350
DMA Address Control Register (DACR) ......................................................... 278
DMA Module Request Select Register (DMRSR) ........................................... 284
Address Modes ................................................................................................. 286
Transfer Modes ................................................................................................. 290
Activation Sources............................................................................................ 295
Bus Access Modes ............................................................................................ 297
Extended Repeat Area Function ....................................................................... 299
Address Update Function using Offset ............................................................. 301
Register during DMA Transfer ......................................................................... 306
Priority of Channels .......................................................................................... 311
DMA Basic Bus Cycle...................................................................................... 313
Bus Cycles in Dual Address Mode ................................................................... 314
Bus Cycles in Single Address Mode................................................................. 323
CPU Priority Control Function Over DMAC ................................................... 331
Bus Arbitration among DMAC and Other Bus Masters ................................... 332
DMAC Register Access During Operation....................................................... 336
Settings of Module Stop Function .................................................................... 336
Activation by DREQ Falling Edge ................................................................... 336
Acceptation of Activation Source ..................................................................... 337
DTC Mode Register A (MRA) ......................................................................... 342
DTC Mode Register B (MRB).......................................................................... 343
DTC Source Address Register (SAR)............................................................... 345
DTC Destination Address Register (DAR)....................................................... 345
DTC Transfer Count Register A (CRA) ........................................................... 346
DTC Transfer Count Register B (CRB)............................................................ 346
DTC enable registers A to H (DTCERA to DTCERH) .................................... 347
DTC Control Register (DTCCR) ...................................................................... 348
DTC Vector Base Register (DTCVBR)............................................................ 349
Rev. 2.00 Sep. 16, 2009 Page xv of xxviii

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