R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 55
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- Current page: 55 of 1070
- Download datasheet (6Mb)
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward
compatible with the H8/300, H8/300H, and H8S CPUs.
The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space,
and is ideal for a realtime control system.
2.1
• Upward-compatible with H8/300, H8/300H, and H8S CPUs
• Sixteen 16-bit general registers
• 87 basic instructions
• Eleven addressing modes
Can execute object programs of these CPUs
Also usable as sixteen 8-bit registers or eight 32-bit registers
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Bit field transfer instructions
Powerful bit-manipulation instructions
Bit condition branch instructions
Multiply-and-accumulate instruction
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]
Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B),
Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @−ERn,
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or
Memory indirect [@@aa:8]
Extended memory indirect [@@vec:7]
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]
@ERn+, or @ERn−]
@(ERn.L,PC)]
Features
Section 2 CPU
Rev. 2.00 Sep. 16, 2009 Page 25 of 1036
REJ09B0414-0200
Section 2 CPU
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