R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 776
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Section 19 ∆Σ A/D Converter
19.3.2
DSADDR0 to DSADDR5 are 16-bit read-only registers for storing the results of A/D conversion.
One register is provided for each analog input channel, and when A/D conversion on a channel is
completed, the result of conversion is stored in the corresponding register. Data stored in each
register are retained until the next round of A/D conversion on that channel ends and the new
result is stored.
DSADDR registers can be read by the CPU at any time, but cannot be written to.
The A/D-converted data is stored in bit 15 to bit 0 as a signed binary number (two's complement).
Bit 15 holds the MSB and bit 0 the LSB.
19.3.3
DSADCSR controls A/D conversion and interrupts and selects analog input channels.
When writing to the register to change the settings of bits SCANE and CH5 to CH0, bit ADST
must be clear.
Rev. 2.00 Sep. 16, 2009 Page 746 of 1036
REJ09B0414-0200
Bit
Bit Name
Initial Value:
R/W:
Bit
Bit Name
Initial Value:
R/W:
Note: * Only 0 can be written here, to clear the flag.
Bit
Bit Name
Initial Value:
R/W:
∆Σ A/D Data Registers 0 to 5 (DSADDR0 to DSADDR5)
∆Σ A/D Control/Status Register (DSADCSR)
15
R
0
R/(W)*
ADF
15
R
0
7
0
14
R
0
13
R
0
ADIE
R/W
14
R
0
6
0
12
R
0
11
R
0
ADST
CH5
R/W
R/W
13
0
5
0
10
R
0
R
9
0
CH4
R/W
12
R
0
4
0
R
8
0
R
7
0
SCANE
R/W
CH3
R/W
11
0
3
0
R
6
0
R
5
0
CH2
R/W
10
R
0
2
0
R
4
0
R
3
0
TRGS1
R/W
CH1
R/W
9
0
1
0
R
2
0
R
1
0
TRGS0
R/W
CH0
R/W
8
0
0
0
R
0
0
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