R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 373

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.2.2
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Bit Name
CHNE
CHNS
DISEL
DTS
DTC Mode Register B (MRB)
Undefined
CHNE

7
Initial
Value
Undefined 
Undefined 
Undefined 
Undefined 
Undefined
CHNS

6
Undefined
R/W
DISEL

5
Description
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see section
10.5.7, Chain Transfer. The chain transfer condition is
selected by the CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends. When
this bit is set to 0, a CPU interrupt request is only
generated when the specified number of data transfer
ends.
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Undefined
DTS

4
Undefined
DM1

3
Rev. 2.00 Sep. 16, 2009 Page 343 of 1036
Section 10 Data Transfer Controller (DTC)
Undefined
DM0

2
Undefined


1
REJ09B0414-0200
Undefined


0