R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 133
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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6.1
• Two interrupt control modes
• Priority can be assigned by the interrupt priority register (IPR)
• Independent vector addresses
• Seventeen external interrupts
• DTC and DMAC control
• CPU priority control function
Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the
interrupt control register (INTCR).
IPR provides for setting interrupt priory. Eight levels can be set for each module for all
interrupts except for the interrupt requests listed below. The following eight interrupt requests
are given priority of 8, therefore they are accepted at all times.
NMI
Illegal instruction
Trace
Trap instruction
CPU address error
DMA address error (occurred in the DTC and DMAC)
Sleep instruction
Break interrupt
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ15 to IRQ0.
DTC and DMAC can be activated by means of interrupts.
The priority levels can be assigned to the CPU, DTC, and DMAC. The priority level of the
CPU can be automatically assigned on an exception generation. Priority can be given to the
CPU interrupt exception handling over that of the DTC and DMAC transfer.
Features
Section 6 Interrupt Controller
Rev. 2.00 Sep. 16, 2009 Page 103 of 1036
Section 6 Interrupt Controller
REJ09B0414-0200
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