IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
HC11
MC68HC11D3
Technical Data
For More Information On This Product,
Go to: www.freescale.com

MC68HC11E0CFNE3 Summary of contents

  • Page 1

    ... Freescale Semiconductor, Inc. HC11 MC68HC11D3 Technical Data For More Information On This Product, Go to: www.freescale.com ...

  • Page 2

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 3

    ... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 and 2 2.2 Reset (RESET 2-2 2.3 Crystal Driver and External Clock Input (XTAL, EXTAL 2-3 2.4 E-Clock Output ( 2-4 2.5 Interrupt Request (IRQ 2-4 2.6 Non-Maskable Interrupt (XIRQ 2-4 2 ...

  • Page 4

    ... Freescale Semiconductor, Inc. Paragraph Table of Contents (Cont.) Number OPERATING MODES AND ON-CHIP MEMORY 4.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2 Expanded Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.3 Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.4 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1 Priority and Mode Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4 ...

  • Page 5

    ... Freescale Semiconductor, Inc. Paragraph Table of Contents (Cont.) Number 6.4 Port 6-2 6.5 Parallel I/O Control Register (PIOC 6-4 SERIAL COMMUNICATIONS INTERFACE 7.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4 Wake-up Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7 ...

  • Page 6

    ... Freescale Semiconductor, Inc. Paragraph Table of Contents (Cont.) Number 9.3.9 Timer Interrupt Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.10 Timer Interrupt Flag 2 Register 9-12 9.4 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.1 Timer Interrupt Flag 2 Register 9-13 9.4.2 Pulse Accumulator Control Register 9-14 9.5 Computer Operating Properly Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . 9-15 9 ...

  • Page 7

    ... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 1-1 MC68HC11D3 Block Diagram ........................................................................ 1-2 2-1 Pin Assignments for 44-Pin PLCC ................................................................. 2-1 2-2 Pin Assignments for 40-Pin DIP ..................................................................... 2-2 2-3 External Reset Circuit ..................................................................................... 2-3 2-4 Common Crystal Connections ........................................................................ 2-3 2-5 External Oscillator Connections ..................................................................... 2-4 2-6 One Crystal Driving Two MCUs ...

  • Page 8

    ... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure A-10 SPI Master Timing (CPHA = 1) .................................................................... A-12 A-11 SPI Slave Timing (CPHA = 0) ...................................................................... A-13 A-12 SPI Slave Timing (CPHA = 1) ...................................................................... A-13 B-1 40-Pin DIP ...................................................................................................... B-1 B-2 44-Pin PLCC .................................................................................................. B-2 B-3 44-Pin QFP ..................................................................................................... B-3 For More Information On This Product, ...

  • Page 9

    ... Freescale Semiconductor, Inc. Table 2-1 Port Signal Functions............................................................................................. 2-6 3-2 Instruction Set........................................................................................................ 3-8 4-1 Register and Control Bit Assignments ................................................................. 4-4 4-2 Hardware Mode Select Summary.......................................................................... 4-6 4-3 RAM Mapping ........................................................................................................ 4-9 4-4 Register Mapping................................................................................................... 4-9 5-1 COP Time-out........................................................................................................ 5-2 5-2 Reset Cause, Reset Vector, and Operating Mode ................................................ 5-4 5-3 Highest Priority Interrupt Selection ...

  • Page 10

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 11

    ... Freescale Semiconductor, Inc. The MC68HC11D3 and MC68HC11D0 are ROM-based high-performance microcon- trollers (MCUs) based on the MC68HC11E9 design. Members of the Dx series are de- rived from the same mask and feature a high speed multiplexed bus capable of running MHz, and a fully static design that allows operations at frequencies to dc ...

  • Page 12

    ... Freescale Semiconductor, Inc. MODB/ MODA/ LIR V XTAL EXTAL STBY OSCILLATOR MODE CONTROL CLOCK LOGIC BUS EXPANSION ADDRESS TIMER SYSTEM CONTROL PORT A PORT B Figure 1-1 MC68HC11D3 Block Diagram 1-2 For More Information On This Product, E IRQ/ XIRQ RESET INTERRUPT LOGIC CPU ADDRESS/DATA STROBE AND HANDSHAKE ...

  • Page 13

    The MC68HC11D3 is available packaged as a 40-pin dual in-line package (DIP), a 44- pin plastic leaded chip carrier (PLCC 44-pin quad flat pack (QFP). Most pins on this MCU serve two or more functions, as described in ...

  • Page 14

    ... Freescale Semiconductor, Inc. PC0/ADDR0 PC1/ADDR1 PC2/ADDR2 PC3/ADDR3 PC4/ADDR4 PC5/ADDR5 PC6/ADDR6 PC7/ADDR7 XIRQ/V PD7/R/W PD6/AS RESET PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS Figure 2-2 Pin Assignments for 40-Pin DIP 2 and Power is supplied to the MCU through ground available on the 44-pin PLCC additional ground pin that ...

  • Page 15

    ... Freescale Semiconductor, Inc. constant can cause the device to misinterpret the type of reset that occurred. Refer to SECTION 5 RESETS AND INTERRUPTS for further information. Figure 2-3 illustrates a reset circuit that uses an external switch. Use a low voltage interrupt circuit, however, to prevent corruption of RAM RESET ...

  • Page 16

    ... Freescale Semiconductor, Inc. EXTAL MCU XTAL Figure 2-5 External Oscillator Connections EXTAL 10 M FIRST MCU XTAL * THIS VALUE INCLUDES ALL STRAY CAPACITANCES. Figure 2-6 One Crystal Driving Two MCUs 2.4 E-Clock Output ( the output connection for the internally generated E clock. The signal from E is used as a timing reference ...

  • Page 17

    ... Freescale Semiconductor, Inc. sensitive, it can be connected to a multiple-source wired-OR network with an external pullup resistor XIRQ is often used as a power loss detect interrupt. DD Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be config- ured for level-sensitive operation if there is more than one source of IRQ interrupt), each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs ...

  • Page 18

    ... Freescale Semiconductor, Inc. 2.10 Port Signals In the 44-pin PLCC package, 32 input/output lines are arranged into four 8-bit ports and D. The lines of ports B, C, and D are fully bidirectional. Each of these four ports serves a purpose other than I/O, depending on the operating mode or peripheral functions selected ...

  • Page 19

    ... Freescale Semiconductor, Inc. 2.10.1 Port A Port A can be read at any time. Inputs return the pin level; outputs return the pin driver input level. If written, port A stores the data in an internal latch. It drives the pins only if they are configured as outputs. Writes to port A do not change the pin state when the pins are configured for timer output compares ...

  • Page 20

    ... Freescale Semiconductor, Inc. output port suitable for wired-OR operation. In wired-OR mode (a port C bit is at logic level zero actively driven low by the N-channel driver. When a port C bit is at logic level one, the associated pin has high impedance, as neither the N- nor the P-channel devices are active ...

  • Page 21

    ... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT This section presents information on M68HC11 central processing unit (CPU) archi- tecture, data types, addressing modes, the instruction set, and special operations, such as subroutine calls and interrupts. The CPU is designed to treat all peripheral, I/O, and memory locations identically as addresses in the 64 Kbyte memory map ...

  • Page 22

    ... Freescale Semiconductor, Inc. 3.1.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and re- sults of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumu- lator D. Although most operations can use accumulators interchangeably, the ...

  • Page 23

    ... Freescale Semiconductor, Inc. JSR, JUMP TO SUBROUTINE MAIN PROGRAM SP PC $9D = JSR SP+1 DIRECT dd SP+2 RTN NEXT MAIN INSTR. SP+3 MAIN PROGRAM SP+4 PC $AD = JSR SP+5 INDEXED SP+6 RTN NEXT MAIN INSTR. SP+7 SP+8 MAIN PROGRAM SP+9 PC $18 = PRE INDEXED, Y $AD = JSR RTN ff NEXT MAIN INSTR ...

  • Page 24

    ... Freescale Semiconductor, Inc. When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine (BSR) instruction, the address of the instruction after the JSR or BSR is automatically pushed onto the stack, least significant byte first. When the subroutine is finished, a return from subroutine (RTS) instruction is executed. The RTS pulls the previously stacked return address from the stack, and loads it into the program counter ...

  • Page 25

    ... Freescale Semiconductor, Inc. tions. Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.1.6.2 Overflow (V) The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V bit is cleared. 3.1.6.3 Zero (Z) The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is zero ...

  • Page 26

    ... Freescale Semiconductor, Inc. terrupt occurred. The X interrupt mask bit is set only by hardware (or acknowledge cleared only by program instruction (TAP, where the associated bit RTI, where bit 6 of the value loaded into the CCR from the stack has been cleared). There is no hardware action for clearing X. ...

  • Page 27

    ... Freescale Semiconductor, Inc. to proceed. The effective address can be specified within an instruction can be calculated. 3.4.1 Immediate In the immediate addressing mode an argument is contained in the byte(s) immediate- ly following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on. There are two-, three-, and four- (if prebyte is required) byte immediate instructions ...

  • Page 28

    ... Freescale Semiconductor, Inc. 3.5 Instruction Set Refer to Table 3-2, which shows all the M68HC11 instructions in all possible address- ing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Table 3-2 Instruction Set (Sheet ...

  • Page 29

    ... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description BCLR (opr) Clear Bit(s) M • (mm) M (msk) BCS (rel) Branch if Carry ? Set BEQ (rel) Branch Zero BGE (rel) Branch Zero BGT (rel) Branch if > Zero BHI (rel) Branch Higher BHS (rel) ...

  • Page 30

    ... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description CLRA Clear 0 A Accumulator A CLRB Clear 0 B Accumulator B CLV Clear Overflow 0 V Flag CMPA (opr) Compare – M Memory CMPB (opr) Compare – M Memory COM (opr) Ones $FF – Complement Memory Byte ...

  • Page 31

    ... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description INC (opr) Increment Memory Byte INCA Increment Accumulator A INCB Increment Accumulator B INS Increment Stack Pointer INX Increment Index Register X INY Increment Index Register Y JMP (opr) Jump See Figure 3–2 JSR (opr) Jump to See Figure 3– ...

  • Page 32

    ... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description LSRB Logical Shift Right LSRD Logical Shift Right Double MUL Multiply NEG (opr) Two’s 0 – Complement Memory Byte NEGA Two’s 0 – Complement A NEGB Two’s 0 – Complement B NOP ...

  • Page 33

    ... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description SBCA (opr) Subtract with A – M – Carry from A SBCB (opr) Subtract with B – M – Carry from B SEC Set Carry 1 C SEI Set Interrupt 1 I Mask SEV Set Overflow 1 V Flag ...

  • Page 34

    ... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description TSX Transfer Stack Pointer to X TSY Transfer Stack Pointer to Y TXS Transfer – Stack Pointer TYS Transfer – Stack Pointer WAI Wait for Stack Regs & WAIT Interrupt XGDX Exchange D ...

  • Page 35

    ... Freescale Semiconductor, Inc. OPERATING MODES AND ON-CHIP MEMORY This section contains information about the modes that define MC68HC11D3 operat- ing conditions, and about the on-chip memory that allows the MCU to be configured for various applications. 4.1 Operating Modes The values of the mode select inputs MODB and MODA during reset determine the operating mode ...

  • Page 36

    ... Freescale Semiconductor, Inc. PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AS R/W E MCU Figure 4-1 Address/Data Demultiplexing 4.1.3 Special Test Mode Special test, a variation of the expanded multiplexed mode, is primarily used during Motorola's internal production testing; however accessible for programming the CONFIG register, and supporting emulation and debugging during development ...

  • Page 37

    ... Freescale Semiconductor, Inc. 4.2 Memory Map The operating mode determines memory mapping and whether memory is addressed on- or off-chip. Refer to Figure 4-2, which illustrates the memory maps for each of the four modes of operation. Memory locations for on-chip resources are the same for both expanded multiplexed and single-chip modes ...

  • Page 38

    ... Freescale Semiconductor, Inc. Table 4-1 Register and Control Bit Assignments Bit 7 6 $0000 PA7 PA6 PA5 $0001 $0002 CWOM $0003 PC7 PC6 PC5 $0004 PB7 PB6 PB5 $0005 $0006 DDB7 DDB6 DDB5 $0007 DDC7 DDC6 DDC5 $0008 PD7 PD6 PD5 $0009 ...

  • Page 39

    ... Freescale Semiconductor, Inc. Table 4-1 Register and Control Bit Assignments (Continued) Bit 7 6 $002B TCLR 0 SCP1 $002C R8 T8 $002D TIE TCIE RIE $002E TDRE TC RDRF $002F R7/T7 R6/T6 R5/T5 $0030 to $0038 $0039 0 0 IRQE $003A Bit 7 6 $003B $003C RBOOT SMOD ...

  • Page 40

    ... Freescale Semiconductor, Inc. In the second method, the MODB/V backup or from a second power supply, as shown in Figure 4-3. Using the MODB/ V pin may require external hardware, but can be justified when a significant STBY amount of external circuitry is operating from V contents, reset must be held low whenever V to SECTION 5 RESETS AND INTERRUPTS ...

  • Page 41

    ... Freescale Semiconductor, Inc. HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous Bit 7 6 RBOOT SMOD RESET: — — The values of the RBOOT, SMOD, IRVNE, and MDA at reset depend on the mode dur- ing initialization. Refer to Table 4-2. RBOOT — Read Bootstrap ROM Has meaning only when the SMOD bit is a one (special bootstrap mode or special test mode) ...

  • Page 42

    ... Freescale Semiconductor, Inc. Mode IRVNE Out of Reset Single-Chip Expanded Boot Special Test PSEL[3:0] — Priority Select Bits Refer to SECTION 5 RESETS AND INTERRUPTS. 4.2.2 System Initialization Registers and bits that control initialization and the basic configuration of the MCU are protected against writes except under special circumstances. The protection mecha- nism, overridden in special operating modes, permits writing these bits only within the first 64 bus cycles after any reset, and then only once after each reset ...

  • Page 43

    ... Freescale Semiconductor, Inc. In expanded mode, ROM is located at $7000–$7FFF out of reset. In all other modes, ROM is located at $F000–$FFFF. 4.2.2.2 INIT Register The internal registers used to control the operation of the MCU can be relocated on 4K boundaries within the memory space with the use of INIT. This 8-bit special-purpose register can change the default locations of the RAM and control registers within the MCU memory map ...

  • Page 44

    ... Freescale Semiconductor, Inc. 4.2.2.3 OPTION Register The 8-bit special-purpose OPTION register sets internal system configuration options during initialization. The time protected control bits, IRQE, DLY, and CR[1:0] can be written to only once after a reset and then they become read-only. This minimizes the possibility of any accidental changes to the system configuration. OPTION — ...

  • Page 45

    ... Freescale Semiconductor, Inc. RESETS AND INTERRUPTS Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current instruction and forces the program counter to a known starting address ...

  • Page 46

    ... Freescale Semiconductor, Inc. COP is enabled, the software is responsible for keeping a free-running watchdog timer from timing out. When the software is no longer being executed in the intended se- quence, a system reset is initiated. The state of the NOCOP bit in the CONFIG register determines whether the COP sys- tem is enabled or disabled ...

  • Page 47

    ... Freescale Semiconductor, Inc. Semiconductor wafer processing causes variations of the RC time-out values between individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using the clock monitor function when the E clock is below 200 kHz is not recommended. ...

  • Page 48

    ... Freescale Semiconductor, Inc. 5.1.6 CONFIG Register CONFIG — Configuration Control Register Bit RESET Bits [7:4] and 0 — Not implemented Always read zero NOCOP — COP System Disable This bit is cleared out of reset in normal modes, enabling the COP system set out of reset in special modes. NOCOP is writable once in normal modes and at any time in special modes ...

  • Page 49

    ... Freescale Semiconductor, Inc. 5.2.3 Parallel I/O When a reset occurs in expanded multiplexed operating modes, the pins used for par- allel I/O are dedicated to the expansion bus. In single-chip and bootstrap modes, all ports are parallel I/O data ports. In expanded multiplexed and test modes, ports B, C, ...

  • Page 50

    ... Freescale Semiconductor, Inc. 5.2.7 COP The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis- ter is clear, and disabled if NOCOP is set. The COP rate is set for the shortest duration time-out. 5.2.8 SCI The reset condition of the SCI system is independent of the operating mode. At reset, the SCI baud rate is indeterminate and must be established by a software write to the BAUD register ...

  • Page 51

    ... Freescale Semiconductor, Inc. The maskable interrupt sources have the following priority arrangement: 1. IRQ 2. Real-time interrupt 3. Timer input capture 1 4. Timer input capture 2 5. Timer input capture 3 6. Timer output compare 1 7. Timer output compare 2 8. Timer output compare 3 9. Timer output compare 4 10 ...

  • Page 52

    ... Freescale Semiconductor, Inc. The IRVNE control bit allows internal read accesses to be available on the external data bus during factory testing or emulation. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information. PSEL[3:0] — Priority Select Bits These bits select one interrupt source to be elevated above all other I-bit-related sources and can be written to only while the I bit in the CCR is set (interrupts disabled) ...

  • Page 53

    ... Freescale Semiconductor, Inc. Table 5-4 Interrupt and Reset Vector Assignments Vector Address FFC0, C1 — FFD4, D5 Reserved FFD6, D7 SCI Serial System FFD8, D9 SPI Serial Transfer Complete FFDA, DB Pulse Accumulator Input Edge FFDC, DD Pulse Accumulator Overflow FFDE, DF Timer Overflow FFE0, E1 Timer Input Capture 4/Output Compare 5 ...

  • Page 54

    ... Freescale Semiconductor, Inc. Table 5-5 Stacking Order on Entry to Interrupts Memory Location SP – –2 SP – – – – – – 8 5.4.2 Non-Maskable Interrupt Request XIRQ Non-maskable interrupts are useful because they can always interrupt CPU opera- tions. The most common use for such an interrupt is for serious system problems, such as program runaway or power failure ...

  • Page 55

    ... Freescale Semiconductor, Inc. The stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode. 5.4.4 Software Interrupt SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhib- ited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit, once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or until user software clears the I bit in the CCR ...

  • Page 56

    ... Freescale Semiconductor, Inc. HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES EXTERNAL RESET LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) 1A Figure 5-1 Processing Flow out of Reset ( 5-12 For More Information On This Product, CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER ...

  • Page 57

    ... Freescale Semiconductor, Inc. STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF6, $FFF7 RESTORE CPU REGISTERS FROM STACK Figure 5-1 Processing Flow out of Reset ( TECHNICAL DATA For More Information On This Product, ...

  • Page 58

    ... Freescale Semiconductor, Inc. BEGIN X BIT YES IN CCR SET ? NO HIGHEST YES PRIORITY INTERRUPT ? NO YES IRQ ? NO YES RTII = YES IC1I = YES IC2I = YES IC3I = YES OC1I = Figure 5-2 Interrupt Priority Resolution ( 5-14 For More Information On This Product, YES XIRQ PIN SET X BIT IN CCR ...

  • Page 59

    ... Freescale Semiconductor, Inc OC2I = OC3I = OC4I = OC5I = TOI = PAOVI = PAII = SPIE = 1? N SCI Y INTERRUPT? SEE FIGURE 9–7 N Figure 5-2 Interrupt Priority Resolution ( TECHNICAL DATA For More Information On This Product, Y FLAG FETCH VECTOR OC2F = 1? $FFE6, $FFE7 N Y FLAG FETCH VECTOR OC3F = 1 $FFE4, $FFE5 ...

  • Page 60

    ... Freescale Semiconductor, Inc. BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 5-3 Interrupt Source Resolution within SCI 5.5 Low-Power Operation Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The WAIT condition suspends processing and reduces power consumption to an interme- diate level ...

  • Page 61

    ... Freescale Semiconductor, Inc. nals driving on-chip peripheral functions can be shut down. The CPU is always shut down during WAIT. While in the wait state, the address/data bus repeatedly runs read cycles to the address where the CCR contents were stacked. The MPU leaves the wait state when it senses any interrupt that has not been masked ...

  • Page 62

    ... Freescale Semiconductor, Inc. 5-18 For More Information On This Product, RESETS AND INTERRUPTS Go to: www.freescale.com TECHNICAL DATA ...

  • Page 63

    ... Freescale Semiconductor, Inc. The MC68HC11D3 has four 8-bit I/O ports and D. In single-chip and bootstrap modes, all ports are parallel I/O data ports. In expanded multiplexed and test modes, ports B and C, and lines DATA6/AS and DATA7/R/W are a memory expansion bus with port B as the high order address bus, port C as the multiplexed address and data bus the demultiplexing signal, and R/W as the data bus direction control ...

  • Page 64

    ... Freescale Semiconductor, Inc. DDRB — Data Direction Register for Port B Bit 7 6 DDB7 DDB6 RESET DDB[7:0] — Data Direction for Port Corresponding port B pin configured for input only 1 = Corresponding port B pin configured as output 6.3 Port C Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul- tiplexed mode, port C pins are configured as multiplexed address/data pins ...

  • Page 65

    ... Freescale Semiconductor, Inc. PORTD — Port D Data Bit 7 6 PD7 PD6 RESET Alt. Func.: R/W AS DDRD — Data Direction Register for Port D Bit 7 6 DDD7 DDD6 RESET DDD[7:0] — Data Direction for Port D When port general-purpose I/O port, the DDRD register controls the direction of ...

  • Page 66

    ... Freescale Semiconductor, Inc. I4/O5 — Configure TI4/O5 register for IC4 or OC5 0 = OC5 function enabled 1 = IC4 function enabled RTR[1:0] — Real-Time Interrupt (RTI) Rate Refer to SECTION 9 TIMING SYSTEM. 6.5 Parallel I/O Control Register (PIOC) PIOC configures and controls handshake I/O functions in MCUs where this function is available ...

  • Page 67

    ... Freescale Semiconductor, Inc. SERIAL COMMUNICATIONS INTERFACE The serial communications interface (SCI universal asynchronous receiver trans- mitter (UART), one of two independent serial I/O subsystems in the MC68HC11D3. It has a standard nonreturn to zero (NRZ) format (one start, eight or nine data, and one stop bit). Several baud rates are available. The SCI transmitter and receiver are inde- pendent, but use the same data format and bit rate ...

  • Page 68

    ... Freescale Semiconductor, Inc. TRANSMITTER BAUD RATE SCDR Tx BUFFER CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 7-1 SCI Transmitter Block Diagram 7.3 Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers parallel receive data register (SCDR complete word ...

  • Page 69

    ... Freescale Semiconductor, Inc. recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. RECEIVER BAUD RATE CLOCK DDD0 PIN BUFFER PD0 ...

  • Page 70

    ... Freescale Semiconductor, Inc. 7.4 Wake-up Feature The wake-up feature reduces SCI service overhead in multiple receiver systems. Soft- ware for each receiver evaluates the first character of each message. The receiver is placed in wakeup mode by writing a one to the RWU bit in the SCCR2 register. While RWU is one, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set) ...

  • Page 71

    ... Freescale Semiconductor, Inc. 7.5 SCI Error Detection Three error conditions, SCDR overrun, received bit noise, and framing can occur dur- ing generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial com- munications status register (SCSR) indicate if one of these error conditions exists. The overrun error (OR) bit is set when the next byte is ready to be transferred from the re- ceive shift register to the SCDR and the SCDR is already full (RDRF bit is set) ...

  • Page 72

    ... Freescale Semiconductor, Inc. T8 — Transmit Data bit bit is set, T8 stores ninth bit in transmit data character. M — Mode (Select Character Format Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit WAKE — Wake-up by Address Mark/Idle 0 = Wake-up by IDLE line recognition 1 = Wake-up by address mark (most significant data bit set) 7 ...

  • Page 73

    ... Freescale Semiconductor, Inc. SBK — Send Break At least one character time of break is queued and sent each time SBK is written to one. More than one break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off, as the baud rate clock edge could occur between writing the one and writing the zero to SBK ...

  • Page 74

    ... Freescale Semiconductor, Inc. NF — Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR Unanimous decision 1 = Noise detected FE — Framing Error FE is set when detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR ...

  • Page 75

    ... Freescale Semiconductor, Inc. Table 7-2 Baud Rate Selects SCR[2:0] Divide Prescaler The prescale bits, SCP[1:0], determine the highest baud rate and the SCR[2:0] bits se- lect an additional binary submultiple ( 1 rate. The result of these two dividers in series is the 16 X receiver baud rate clock. The SCR[2:0] bits are not affected by reset and can be changed at any time, although they should not be changed when any SCI transfer is in progress ...

  • Page 76

    ... Freescale Semiconductor, Inc. EXTAL OSCILLATOR AND CLOCK GENERATOR (÷ 4) XTAL E AS Figure 7-3 SCI Baud Rate Diagram 7.7 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present ...

  • Page 77

    ... Freescale Semiconductor, Inc. TDRE and TC flags are normally set when the transmitter is first enabled (TE set to one). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIE is zero, TDRE must be polled ...

  • Page 78

    ... Freescale Semiconductor, Inc. BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 7-4 Interrupt Source Resolution within SCI SERIAL COMMUNICATIONS INTERFACE 7-12 For More Information On This Product, Y RIE = TIE = TCIE = ILIE = to: www.freescale.com VALID SCI REQUEST INT SOURCE RES TECHNICAL DATA ...

  • Page 79

    ... Freescale Semiconductor, Inc. SERIAL PERIPHERAL INTERFACE The serial peripheral interface (SPI), an independent serial communications sub- system, allows the MCU to communicate synchronously with peripheral devices, such as transistor-transistor logic (TTL) shift registers, liquid crystal diode (LCD) display drivers, analog-to-digital converter subsystems, and other microprocessors. The SPI is also capable of inter-processor communication in a multiple master system ...

  • Page 80

    ... Freescale Semiconductor, Inc. INTERNAL MCU CLOCK DIVIDER ÷2 ÷4 ÷16 ÷32 SPI CLOCK (MASTER) SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST Figure 8-1 SPI Block Diagram 8.2 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device ...

  • Page 81

    ... Freescale Semiconductor, Inc. SCK CYCLE # 1 SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT MSB (CPHA = 0) DATA OUT SAMPLE INPUT MSB (CPHA = 1 ) DATA OUT SS (TO SLAVE ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED Figure 8-2 SPI Transfer Format 8.2.1 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR) ...

  • Page 82

    ... Freescale Semiconductor, Inc. 8.3.1 Master In Slave Out MISO is one of two unidirectional serial data signals input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high impedance state if the slave device is not selected. 8.3.2 Master Out Slave In The MOSI line is the second of the two unidirectional serial data signals ...

  • Page 83

    ... Freescale Semiconductor, Inc. indicates that an attempt was made to write data to the SPDR while a transfer was in progress. When the SPI system is configured as a master and the SS input line goes to active low, a mode fault error has occurred — usually because two devices have attempted to act as master at the same time ...

  • Page 84

    ... Freescale Semiconductor, Inc. 8.5.1 Serial Peripheral Control SPCR — Serial Peripheral Control Register Bit 7 6 SPIE SPE RESET SPIE — Serial Peripheral Interrupt Enable 0 = SPI interrupt disabled 1 = SPI interrupt enabled SPE — Serial Peripheral System Enable 0 = SPI off 1 = SPI on DWOM — Port D Wired-OR Mode DWOM affects all six port D pins ...

  • Page 85

    ... Freescale Semiconductor, Inc. 8.5.2 Serial Peripheral Status SPSR — Serial Peripheral Status Register Bit 7 6 SPIF WCOL RESET SPIF — SPI Transfer Complete Flag SPIF is set upon completion of data transfer between the processor and the external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. ...

  • Page 86

    ... Freescale Semiconductor, Inc. SERIAL PERIPHERAL INTERFACE 8-8 For More Information On This Product, Go to: www.freescale.com TECHNICAL DATA ...

  • Page 87

    ... Freescale Semiconductor, Inc. The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programma- ble prescaler. The main timer's programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. Two prescaler control bits select the prescale rate ...

  • Page 88

    ... Freescale Semiconductor, Inc. OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) PRESCALER (÷ 16, 32) SPR[1:0] PRESCALER (÷ 13) SCP[1:0] E÷2 6 E÷2 13 PRESCALER (÷ 16) PR[1:0] TOF TCNT IC/OC Figure 9-1 Timer Clock Divider Chains 9-2 For More Information On This Product, PRESCALER (÷ 4,....128) SCR[2:0] ÷ ...

  • Page 89

    ... Freescale Semiconductor, Inc. 4.0 MHz Control 1.0 MHz Bits 1000 ns PR[1: count — 1.0 µs overflow — 65.536 count — 4.0 µs overflow — 262. count — 8.0 µs overflow — 524. count — 16.0 µs overflow — 1.049 s 9.1 Timer Structure Figure 9-1 shows the capture/compare system block diagram ...

  • Page 90

    ... Freescale Semiconductor, Inc. PRESCALER — DIVIDE SYSTEM PR1 PR0 CLOCK 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 CLK 16-BIT LATCH TIC1 (HI) ...

  • Page 91

    ... Freescale Semiconductor, Inc. In most cases, input capture edges are asynchronous to the internal timer counter, which is clocked relative to the PH2 clock. These asynchronous capture requests are synchronized to PH2 so that the latching occurs on the opposite half cycle of PH2 from when the timer counter is being incremented. This synchronization process introduces a delay from when the edge occurs to when the counter value is detected ...

  • Page 92

    ... Freescale Semiconductor, Inc. 9.2.2 Timer Input Capture Registers When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel trans- fer. Timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase two clock so that the count value is stable whenever a capture occurs ...

  • Page 93

    ... Freescale Semiconductor, Inc. polarity of the pulse being produced. After a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match. A value representing the width of the pulse is added to the original value, and then writ- ten to the output compare register. Because the pin state changes occur at specific values of the free-running counter, the pulse width can be controlled accurately at the resolution of the free-running counter, independent of software latencies ...

  • Page 94

    ... Freescale Semiconductor, Inc. TOC1–TOC4 — Timer Output Compare $0016 Bit 15 14 $0017 Bit 7 6 $0018 Bit 15 14 $0019 Bit 7 6 $001A Bit 15 14 $001B Bit 7 6 $001C Bit 15 14 $001D Bit 7 6 All TOCx register pairs reset to ones ($FFFF) TI4/O5 — Timer Input Capture 4/Output Compare 5 Refer to 9 ...

  • Page 95

    ... Freescale Semiconductor, Inc. OC1M — Output Compare 1 Mask Bit 7 6 OC1M7 OC1M6 RESET OC1M7–OC1M3 — Output Compare Masks 0 = OC1 is disabled 1 = OC1 is enabled to control the corresponding pin of port A Bits [2:0] — Not implemented; always read zero Set bit(s) to enable OC1 to control corresponding pin(s) of port A. ...

  • Page 96

    ... Freescale Semiconductor, Inc. TCTL1 — Timer Control 1 Bit 7 6 OM2 OL2 RESET OM[2:5] — Output Mode OL[2:5] — Output Level These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to the following table for the coding ...

  • Page 97

    ... Freescale Semiconductor, Inc. polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position. TFLG1 — Timer Interrupt Flag 1 Bit 7 6 OC1F OC2F RESET Clear flags by writing a one to the corresponding bit position(s). OC1F–OC5F — Output Compare x Flag Set each time the counter matches output compare x value I4/O5F — ...

  • Page 98

    ... Freescale Semiconductor, Inc. PR[1:0] — Timer Prescaler Select These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can only be written once, and the write must be within 64 cycles after reset. Refer to Table 9-1 for specific timing values. 9.3.10 Timer Interrupt Flag 2 Register Bits in this register indicate when certain timer system events have occurred ...

  • Page 99

    ... Freescale Semiconductor, Inc. RTR[1: MHz 0 0 2.731 5.461 10.923 21.845 ms The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except by reset. This clock causes the time between successive RTI time- outs constant that is independent of the software latencies associated with flag clearing and service ...

  • Page 100

    ... Freescale Semiconductor, Inc. TFLG2 — Timer Interrupt Flag 2 Bit 7 6 TOF RTIF RESET Clear flags by writing a one to the corresponding bit position(s). TOF — Timer Overflow Interrupt Flag Set when TCNT changes from $FFFF to $0000 RTIF — Real-Time Interrupt Flag The RTIF status bit is automatically set to one at the end of every RTI period. To clear RTIF, write a byte to TFLG2 with bit 6 set. PAOVF — ...

  • Page 101

    ... Freescale Semiconductor, Inc. RTR[1:0] — RTI Interrupt Rate Select These two bits determine the rate at which the RTI system requests interrupts. The RTI system is driven divided by 2 dependent of the timer prescaler. These two control bits select an additional division factor. RTR[1: MHz ...

  • Page 102

    ... Freescale Semiconductor, Inc. E ÷ 64 CLOCK (FROM MAIN TIMER) INPUT BUFFER PA7/ & PAI/OC1 EDGE DETECTION OUTPUT FROM BUFFER MAIN TIMER OC1 PACTL Figure 9-3 Pulse Accumulator Table 9-3 Pulse Accumulator Timing Selected Crystal CPU Clock Cycle Time Pulse Accumulator (in Gated Mode) ...

  • Page 103

    ... Freescale Semiconductor, Inc. 9.6.1 Pulse Accumulator Control Register Four of this register's bits control an 8-bit pulse accumulator system. Another bit en- ables either the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system. PACTL — Pulse Accumulator Control ...

  • Page 104

    ... Freescale Semiconductor, Inc. PACNT — Pulse Accumulator Count Bit 7 6 Bit 7 6 9.6.3 Pulse Accumulator Status and Interrupt Bits The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located within timer registers TMSK2 and TFLG2. PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00 ...

  • Page 105

    ... Freescale Semiconductor, Inc. ELECTRICAL CHARACTERISTICS Rating Supply Voltage Input Voltage Operating Temperature Range MC6811D3 MC6811D3C MC6811D3V MC6811D3M Storage Temperature Range Current Drain per Pin* Excluding V and *One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage caused by high static voltages or electric fields ...

  • Page 106

    ... Freescale Semiconductor, Inc. Table A-3 DC Electrical Characteristics Characteristic Output Voltage (Note 1) All Outputs Except XTAL, RESET ± 10.0 µA LOAD Output High Voltage (Note – 0.8 mA 4.5 V LOAD DD Output Low Voltage I = 1.6 mA 5.0 V LOAD DD Input High Voltage Input Low Voltage I/O Ports, Three-State Leakage PA7, PA3, PB[7:0], PC[7:0], PD[7:0], ...

  • Page 107

    ... Freescale Semiconductor, Inc CLOCKS, STROBES 0.4 Volts INPUTS OUTPUTS ~ TESTING ~ V DD CLOCKS, STROBES 20 INPUTS OUTPUTS TESTING NOTES: 1. Full test loads are applied during all DC electrical tests and AC timing measurements. 2. During AC timing measurements, inputs are driven to 0.4 volts and VDD – 0.8 volts while timing ...

  • Page 108

    ... Freescale Semiconductor, Inc. Characteristic Frequency of Operation E-Clock Period Crystal Frequency External Oscillator Frequency Processor Control SetupTime PCSU cyc Reset Input Pulse Width To Guarantee External Reset Vector Minimum Input Time (Can Be Preempted by Internal Reset) Mode Programming Setup Time Mode Programming Hold Time ...

  • Page 109

    ... Freescale Semiconductor, Inc. Figure A-3 POR and External Reset Timing Diagram ELECTRICAL CHARACTERISTICS TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com A-5 ...

  • Page 110

    ... Freescale Semiconductor, Inc. Figure A-4 STOP Recovery Timing Diagram ELECTRICAL CHARACTERISTICS A-6 For More Information On This Product, Go to: www.freescale.com TECHNICAL DATA ...

  • Page 111

    ... Freescale Semiconductor, Inc. Figure A-5 WAIT Recovery Timing Diagram ELECTRICAL CHARACTERISTICS TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com A-7 ...

  • Page 112

    ... Freescale Semiconductor, Inc. Table A-5 Peripheral Port Timing Characteristic Frequency of Operation (E-Clock Frequency) E-Clock Period Peripheral Data Setup Time MCU Read of Ports and D Peripheral Data Hold Time MCU Read of Ports and D Delay Time, Peripheral Data Write MCU Write to Port A MCU Writes to Ports B, C, and D ...

  • Page 113

    ... Freescale Semiconductor, Inc. Num Characteristic Frequency of Operation (E-Clock Frequency) 1 Cycle Time 2 Pulse Width, E Low 23ns EL cyc 3 Pulse Width, E High cyc 4A E and AS Rise Time 4B E and AS Fall Time 9 Address Hold Time cyc 12 Non-Muxed Address Valid Time to E Rise ...

  • Page 114

    ... Freescale Semiconductor, Inc. E R/W, ADDRESS (NON-MUX) 36 READ ADDRESS/DATA (MULTIPLEXED) WRITE NOTE: Measurement points shown are 20% and 70 Figure A-8 Multiplexed Expansion Bus Timing Diagram ELECTRICAL CHARACTERISTICS A-10 For More Information On This Product ADDRESS 19 ADDRESS to: www.freescale.com DATA 21 DATA MUX BUS TIM TECHNICAL DATA ...

  • Page 115

    ... Freescale Semiconductor, Inc. Table A-7 Serial Peripheral Interface Timing Num Characteristic Operating Frequency Master Slave 1 Cycle Time Master Slave 2 Enable Lead Time Master (Note 2) Slave 3 Enable Lag Time Master (Note 2) Slave 4 Clock (SCK) High Time Master Slave 5 Clock (SCK) Low Time ...

  • Page 116

    ... Freescale Semiconductor, Inc held high on master. (INPUT) SCK (CPOL = 0) SEE NOTE (OUTPUT) SCK (CPOL = 1) SEE NOTE (OUTPUT) MISO (INPUT) 10 (ref) MOSI (OUTPUT) 13 NOTE: This first clock edge is generated internally but is not seen at the SCK pin. Figure A-9 SPI Master Timing (CPHA = held high on master ...

  • Page 117

    ... Freescale Semiconductor, Inc. SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SLAVE (OUTPUT) 6 MOSI MSB IN (INPUT) NOTE: Not defined but normally MSB of character just received. Figure A-11 SPI Slave Timing (CPHA = 0) SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT SEE MISO ...

  • Page 118

    ... Freescale Semiconductor, Inc. ELECTRICAL CHARACTERISTICS A-14 For More Information On This Product, Go to: www.freescale.com TECHNICAL DATA ...

  • Page 119

    ... Freescale Semiconductor, Inc. MECHANICAL DATA AND ORDERING INFORMATION B.1 Pin Assignments The MC68HC11D3 is available in the 40-pin DIP, shown in Figure B-1, the 44-pin PLCC, shown in Figure B-2, or the 44-pin quad flat pack (QFP), as shown in Figure B-3. Refer to Table B-1 for ordering information. ...

  • Page 120

    PC4/ADDR4 PC5/ADDR5 PC6/ADDR6 PC7/ADDR7 XIRQ/V PP PD7/R/W PD6/AS RESET IRQ PD0/RxD PD1/TxD B MC68HC(7)11D3 Figure B-2 44-Pin PLCC 39 PB0/ADDR8 PB1/ADDR9 38 37 PB2/ADDR10 36 PB3/ADDR11 35 PB4/ADDR12 PB5/ADDR13 ...

  • Page 121

    PC4/ADDR4 PC5/ADDR5 PC6/ADDR6 PC7/ADDR7 XIRQ/V PP PD7/R/W PD6/AS RESET IRQ PD0/RxD PD1/TxD B.2 Package Dimensions For case outline information check our web site at http://www.motsps.com. B.3 Ordering Information Add the proper suffix, from Table B-1, to the M68HC11- (or 711-) ...

  • Page 122

    ... Freescale Semiconductor, Inc. Figure B-4 M68HC11 Part Number Options MECHANICAL DATA AND ORDERING INFORMATION B-4 For More Information On This Product, Go to: www.freescale.com TECHNICAL DATA ...

  • Page 123

    ... Freescale Semiconductor, Inc. DEVELOPMENT SUPPORT C.1 Development System Tools Freescale has developed tools for use in debugging and evaluating M68HC11 equip- ment. Refer to the following list for those development tools that are available for use with the MC68HC11D3. For information about Freescale and third party development system hardware and software, contact your Freescale sales representative ...

  • Page 124

    ... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...