MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 49

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
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5.2.3 Parallel I/O
5.2.4 Timer
5.2.5 Real-Time Interrupt
5.2.6 Pulse Accumulator
TECHNICAL DATA
When a reset occurs in expanded multiplexed operating modes, the pins used for par-
allel I/O are dedicated to the expansion bus. In single-chip and bootstrap modes, all
ports are parallel I/O data ports. In expanded multiplexed and test modes, ports B, C,
and lines DATA6/AS and DATA7/R/W are a memory expansion bus with port B as a
high-order address bus, port C as a multiplexed address and data bus, AS as the de-
multiplexing signal, and R/as the data bus direction control. The CWOM bit in PIOC is
cleared so that port C is not in wired-OR mode. Port A, bits [0:3] and 7; and ports B,
C, and D are general-purpose I/O at reset and set for input. For this reason the pins
are configured as high impedance upon reset. Port A bits [4:6] are outputs, so high im-
pedance protection is not necessary.
During reset, the timing system is initialized to a count of $0000. The prescaler bits are
cleared, and all output compare registers are initialized to $FFFF. All input capture reg-
isters are indeterminate after reset. The output compare 1 mask (OC1M) register is
cleared so that successful OC1 compares do not affect any I/O pins. The other four
output compares are configured so that they do not affect any I/O pins on successful
compares. All input capture edge-detector circuits are configured for capture disabled
operation. The timer overflow interrupt flag and all eight timer function interrupt flags
are cleared. All nine timer interrupts are disabled because their mask bits have been
cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5;
however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not
control the PA3 pin.
The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are
masked. The rate control bits are cleared after reset and can be initialized by software
before the real-time interrupt (RTI) system is used. After reset, a full RTI period elaps-
es before the first RTI interrupt.
The pulse accumulator system is disabled at reset so that the PAI input pin defaults to
being a general-purpose input pin (PA7).
Do not confuse pin function with the electrical state of the pin at reset.
All general-purpose I/O pins configured as inputs at reset are in a
high impedance state. Port data registers reflect the port's functional
state at reset. The pin function is mode dependent.
Freescale Semiconductor, Inc.
For More Information On This Product,
RESETS AND INTERRUPTS
Go to: www.freescale.com
NOTE
5-5

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