IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
nals driving on-chip peripheral functions can be shut down. The CPU is always shut
down during WAIT. While in the wait state, the address/data bus repeatedly runs read
cycles to the address where the CCR contents were stacked. The MPU leaves the wait
state when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if the I bit is set to one and the COP
system is disabled by NOCOP being set to one. Several other systems can also be in
a reduced power consumption state depending on the state of software-controlled
configuration control bits. The SPI system is enabled or disabled by the SPE control
bit. The SCI transmitter is enabled or disabled by the TE bit, and the SCI receiver is
enabled or disabled by the RE bit. Therefore the power consumption in WAIT is de-
pendent on the particular application.
5.5.2 STOP
Executing the STOP instruction while the S bit in the CCR is equal to zero places the
MCU in the STOP condition. If the S bit is not zero, the STOP opcode is treated as a
no-op (NOP). The STOP condition offers minimum power consumption because all
clocks, including the crystal oscillator, are stopped while in this mode. To exit STOP
and resume normal processing, a logic low level must be applied to one of the external
interrupts (IRQ or XIRQ), or to the RESET pin. A pending edge-triggered IRQ can also
bring the CPU out of STOP.
Because all clocks are stopped in this mode, all internal peripheral functions also stop.
The data in the internal RAM is retained as long as V
state and I/O pin levels are static and are unchanged by STOP. Therefore, when an
interrupt comes to restart the system, the MCU resumes processing as if there were
no interruption. If reset is used to restart the system a normal reset sequence results
where all I/O pins and functions are also restored to their initial states.
To use the IRQ pin as a means of recovering from STOP, the I bit in the CCR must be
clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from STOP
regardless of the state of the X bit in the CCR, although the recovery sequence de-
pends on the state of the X bit. If X is set to zero (XIRQ not masked), the MCU starts
up, beginning with the stacking sequence leading to normal service of the XIRQ re-
quest. If X is set to one (XIRQ masked or inhibited), then processing continues with
the instruction that immediately follows the STOP instruction, and no XIRQ interrupt
service is requested or pending.
Because the oscillator is stopped in STOP mode, a restart delay may be imposed to
allow oscillator stabilization upon leaving STOP. If the internal oscillator is being used,
this delay is required; however, if a stable external oscillator is being used, the DLY
control bit can be used to bypass this startup delay. The DLY control bit is set by reset
and can be optionally cleared during initialization. If the DLY equal to zero option is
used to avoid startup delay on recovery from STOP, then reset should not be used as
the means of recovering from STOP, as this causes DLY to be set again by reset, im-
posing the restart delay. This same delay also applies to power-on-reset, regardless
of the state of the DLY control bit, but does not apply to a reset while the clocks are
running.
TECHNICAL DATA
For More Information On This Product,
power is maintained. The CPU
DD
RESETS AND INTERRUPTS
Go to: www.freescale.com
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