IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
In most cases, input capture edges are asynchronous to the internal timer counter,
which is clocked relative to the PH2 clock. These asynchronous capture requests are
synchronized to PH2 so that the latching occurs on the opposite half cycle of PH2 from
when the timer counter is being incremented. This synchronization process introduces
a delay from when the edge occurs to when the counter value is detected. Because
these delays offset each other when the time between two edges is being measured,
the delay can be ignored. When an input capture is being used with an output com-
pare, there is a similar delay between the actual compare point and when the output
pin changes state.
The control and status bits that implement the input capture functions are contained in
the PACTL, TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL reg-
ister. Note that this bit is cleared out of reset. To enable PA3 as the fourth input cap-
ture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth
output compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is set (con-
figuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the
pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register
is acting as IC4.
9.2.1 Timer Control 2 Register
Use the control bits of this register to program input capture functions to detect a par-
ticular edge polarity on the corresponding timer input pin. Each of the input capture
functions can be independently configured to detect rising edges only, falling edges
only, any edge (rising or falling), or to disable the input capture function. The input cap-
ture functions operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count cycle.
TCTL2 — Timer Control 2
Bit 7
6
EDG4B
EDG4A
RESET:
0
0
EDGxB and EDGxA — Input Capture Edge Control
There are four pairs of these bits. Each pair is cleared to zero by reset and must be
encoded to configure the corresponding input capture edge detector circuit. IC4 func-
tions only if the I4/O5 bit in the PACTL register is set. Refer to Table 9-2 for timer con-
trol configuration.
Table 9-2 Timer Control Configuration
EDGxB
0
0
1
1
TECHNICAL DATA
For More Information On This Product,
5
4
3
EDG1B
EDG1A
EDG2B
0
0
0
EDGxA
Configuration
0
Capture disabled
1
Capture on rising edges only
0
Capture on falling edges only
1
Capture on any edge
TIMING SYSTEM
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$0021
2
1
Bit 0
EDG2A
EDG3B
EDG3A
0
0
0
9-5