IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
Characteristic
Frequency of Operation
E-Clock Period
Crystal Frequency
External Oscillator Frequency
Processor Control SetupTime
t
= 1/4 t
+ 50 ns
PCSU
cyc
Reset Input Pulse Width
To Guarantee External Reset Vector
Minimum Input Time
(Can Be Preempted by Internal Reset)
Mode Programming Setup Time
Mode Programming Hold Time
Interrupt Pulse Width,
IRQ Edge-Sensitive Mode
PW
= t
+ 20 ns
IRQ
cyc
Wait Recovery Startup Time
Timer Pulse Width,
Input Capture Pulse
Accumulator Input
PW
= t
+ 20 ns
TIM
cyc
NOTES:
1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four
clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
2. All timing is shown with respect to 20% V
1
PA[2:0]
2
PA[2:0]
1,3
PA7
PW
TIM
2,3
PA7
NOTES:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
A-4
For More Information On This Product,
Table A-4 Control Timing
Symbol
1.0 MHz
Min
Max
f
dc
1.0
o
t
1000
cyc
f
4.0
XTAL
4 f
dc
4.0
o
t
300
PCSU
PW
RSTL
8
1
t
2
MPS
t
10
MPH
PW
1020
IRQ
t
4
WRS
PW
1020
TIM
and 70% V
, unless otherwise noted.
DD
DD
Figure A-2 Timer Inputs
ELECTRICAL CHARACTERISTICS
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2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
dc
2.0
dc
3.0
MHz
500
333
ns
8.0
12.0
MHz
dc
8.0
dc
12.0
MHz
175
133
ns
8
8
t
cyc
1
1
t
cyc
2
2
t
cyc
10
10
ns
520
353
ns
4
4
t
cyc
520
353
ns
TIMER INPUTS TIM
TECHNICAL DATA