IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
PORTD — Port D Data
Bit 7
6
PD7
PD6
RESET:
0
0
Alt. Func.:
R/W
AS
DDRD — Data Direction Register for Port D
Bit 7
6
DDD7
DDD6
RESET:
0
0
DDD[7:0] — Data Direction for Port D
When port D is a general-purpose I/O port, the DDRD register controls the direction of
the I/O pins as follows:
0 = Configures the corresponding port D pin for input
1 = Configures the corresponding port D pin for output
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W outputs.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave
select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master
mode, DDD5 affects port D bit 5 as follows:
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be
inputs, then they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI
expects port D bits 2, 3, and 4 to be outputs, they are outputs only if DDRD bits 2, 3,
and 4 are set.
PACTL — Pulse Accumulator Control
Bit 7
6
DDRA7
PAEN
RESET:
0
0
DDRA7 — Data Direction Control for Port A Bit 7
Refer to SECTION 9 TIMING SYSTEM.
PAEN — Pulse Accumulator System Enable
Refer to SECTION 9 TIMING SYSTEM.
PAMOD — Pulse Accumulator Mode
Refer to SECTION 9 TIMING SYSTEM.
PEDGE — Pulse Accumulator Edge Control
Refer to SECTION 9 TIMING SYSTEM.
DDRA3 — Data Direction for Port A Bit 3
Overridden if an output compare function is configured to control the PA3 pin.
0 = Input only
1 = Output
TECHNICAL DATA
For More Information On This Product,
5
4
3
PD5
PD4
PD3
0
0
0
SCK
MOSI
5
4
3
DDD5
DDD4
DDD3
0
0
0
5
4
3
PAMOD
PEDGE
DDRA3
0
0
0
PARALLEL I/O
Go to: www.freescale.com
$0008
2
1
Bit 0
PD2
PD1
PD0
0
0
0
MISO
TxD
RxD
$0009
2
1
Bit 0
DDD2
DDD1
DDD0
0
0
0
$0026
2
1
Bit 0
I4/O5
RTR1
RTR0
0
0
0
6-3