MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 73

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
SCSR — SCI Status Register
SBK — Send Break
7.6.4 Serial Communication Status Register (SCSR)
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
TECHNICAL DATA
RESET:
At least one character time of break is queued and sent each time SBK is written to
one. More than one break may be sent if the transmitter is idle at the time the SBK bit
is toggled on and off, as the baud rate clock edge could occur between writing the one
and writing the zero to SBK.
The SCSR provides inputs to the interrupt logic circuits for generation of the SCI sys-
tem interrupt.
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with
TDRE set and then writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break transmission
in progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF
flag by reading SCSR with RDRF set and then reading SCDR.
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD
line has been active and becomes idle again. The IDLE flag is inhibited when RWU =
1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR.
OR is set if a new character is received before a previously received character is read
from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR.
0 = Break generator off
1 = Break codes generated as long as SBK = 1
0 = SCDR busy
1 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
0 = RxD line is active
1 = RxD line is idle
0 = No overrun
1 = Overrun detected
TDRE
Bit 7
1
TC
Freescale Semiconductor, Inc.
6
1
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
RDRF
Go to: www.freescale.com
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
$002E
Bit 0
0
0
7-7

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