IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
9.2.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running counter
value is transferred into the input capture register pair as a single 16-bit parallel trans-
fer. Timer counter value captures and timer counter incrementing occur on opposite
half-cycles of the phase two clock so that the count value is stable whenever a capture
occurs. The TICx registers are not affected by reset. Input capture values can be read
from a pair of 8-bit read-only registers. A read of the high-order byte of an input capture
register pair inhibits a new capture transfer for one bus cycle. If a double-byte read in-
struction, such as LDD, is used to read the captured value, coherency is assured.
When a new input capture occurs immediately after a high-order byte read, transfer is
delayed for an additional cycle but the value is not lost.
TIC1–TIC3 — Timer Input Capture
$0010
Bit 15
14
$0011
Bit 7
6
$0012
Bit 15
14
$0013
Bit 7
6
$0014
Bit 15
14
$0015
Bit 7
6
RESET:
9.2.3 Timer Input Capture 4/Output Compare 5 Register
Use TI4/O5 as either an input capture register or an output compare register, depend-
ing on the function chosen for the I4/O5 pin. To enable it as an input capture pin, set
the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To
use it as an output compare register, set the I4/O5 bit to a logic level zero. Refer to 9.6
Pulse Accumulator.
TI4/O5 — Timer Input Capture 4/Output Compare 5
$001E
Bit 15
14
$001F
Bit 7
6
RESET:
9.3 Output Compare
Use the output compare (OC) function to program an action to occur at a specific time
— when the 16-bit counter reaches a specified value. For each of the five output com-
pare functions, there is a separate 16-bit compare register and a dedicated 16-bit com-
parator. The value in the compare register is compared to the value of the free-running
counter on every bus cycle. When the compare register matches the counter value, an
output compare status flag is set. The flag can be used to initiate the automatic actions
for that output compare function.
To produce a pulse of a specific duration, write to the output compare register a value
representing the time the leading edge of the pulse is to occur. The output compare
circuit is configured to set the appropriate output either high or low, depending on the
9-6
For More Information On This Product,
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Input capture registers not affected by reset.
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All I4/O5 register pairs reset to ones ($FFFF).
TIMING SYSTEM
Go to: www.freescale.com
$0010–$0015
9
Bit 8
TIC1 (High)
1
Bit 0
TIC1 (Low)
9
Bit 8
TIC2 (High)
1
Bit 0
TIC2 (Low)
9
Bit 8
TIC3 (High)
1
Bit 0
TIC3 (Low)
$001E, $001F
9
Bit 8
TI4/O5 (High)
1
Bit 0
TI4/O5 (Low)
TECHNICAL DATA