MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 103
Manufacturer Part Number
IC MCU 8BIT 3MHZ 52-PLCC
Specifications of MC68HC11E0CFNE3
Number Of I /o
Program Memory Type
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
No. Of I/o's
Ram Memory Size
No. Of Timers
Embedded Interface Type
Digital Ic Case Style
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
Lead Free Status / Rohs Status
Freescale Semiconductor, Inc.
9.6.1 Pulse Accumulator Control Register
Four of this register's bits control an 8-bit pulse accumulator system. Another bit en-
ables either the OC5 function or the IC4 function, while two other bits select the rate
for the real-time interrupt system.
PACTL — Pulse Accumulator Control
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used
as general-purpose I/O or as an output compare. Note that even when port A bit 7 is
configured as an output, the pin still drives the input to the pulse accumulator. Refer to
SECTION 6 PARALLEL I/O for more information.
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in
the following table:
DDRA3 — Data Direction Register for Port A Bit 3
Refer to SECTION 6 PARALLEL I/O.
I4/O5 — Input Capture 4/Output Compare 5
Refer to 9.2 Input Capture.
RTR[1:0] — RTI Interrupt Rate Selects
Refer to 9.4 Real-Time Interrupt.
9.6.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
For More Information On This Product,
Action on Clock
PAI Falling Edge Increments the Counter.
PAI Rising Edge Increments the Counter.
A Zero on PAI Inhibits Counting.
A One on PAI Inhibits Counting.
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