IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
9.6.1 Pulse Accumulator Control Register
Four of this register's bits control an 8-bit pulse accumulator system. Another bit en-
ables either the OC5 function or the IC4 function, while two other bits select the rate
for the real-time interrupt system.
PACTL — Pulse Accumulator Control
Bit 7
6
DDRA7
PAEN
RESET:
0
0
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used
as general-purpose I/O or as an output compare. Note that even when port A bit 7 is
configured as an output, the pin still drives the input to the pulse accumulator. Refer to
SECTION 6 PARALLEL I/O for more information.
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in
the following table:
PAMOD
0
0
1
1
DDRA3 — Data Direction Register for Port A Bit 3
Refer to SECTION 6 PARALLEL I/O.
I4/O5 — Input Capture 4/Output Compare 5
Refer to 9.2 Input Capture.
RTR[1:0] — RTI Interrupt Rate Selects
Refer to 9.4 Real-Time Interrupt.
9.6.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
TECHNICAL DATA
For More Information On This Product,
5
4
3
PAMOD
PEDGE
DDRA3
0
0
0
PEDGE
Action on Clock
0
PAI Falling Edge Increments the Counter.
1
PAI Rising Edge Increments the Counter.
0
A Zero on PAI Inhibits Counting.
1
A One on PAI Inhibits Counting.
TIMING SYSTEM
Go to: www.freescale.com
$0026
2
1
Bit 0
I4/O5
RTR1
RTR0
0
0
0
9-17