IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
4.2.2.3 OPTION Register
The 8-bit special-purpose OPTION register sets internal system configuration options
during initialization. The time protected control bits, IRQE, DLY, and CR[1:0] can be
written to only once after a reset and then they become read-only. This minimizes the
possibility of any accidental changes to the system configuration.
OPTION — System Configuration Options
Bit 7
6
0
0
RESET:
0
0
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes
Bits [7:6] and 2 — Not implemented
Always read zero
IRQE — IRQ Select Edge Sensitive only
0 = IRQ is configured for level sensitive operation
1 = IRQ is configured for edge sensitive only operation
DLY — Enable Oscillator Startup Delay
0 = The oscillator startup delay coming out of STOP is bypassed and the MCU re-
sumes processing within about four bus cycles.
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
up from the STOP power-saving mode. This delay allows the crystal oscillator
to stabilize.
CME — Clock Monitor Enable
Refer to SECTION 5 RESETS AND INTERRUPTS.
CR[1:0] — COP Timer Rate Select Bits
The internal E clock is first divided by 2
These control bits determine a scaling factor for the watchdog timer. Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
OPERATING MODES AND ON-CHIP MEMORY
4-10
For More Information On This Product,
5
4
3
IRQE*
DLY*
CME
0
1
0
15
before it enters the COP watchdog system.
Go to: www.freescale.com
$0039
2
1
Bit 0
0
CR1*
CR0*
0
0
0
TECHNICAL DATA