IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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JSR, JUMP TO SUBROUTINE
MAIN PROGRAM
SP
PC
$9D = JSR
SP+1
DIRECT
dd
SP+2
RTN
NEXT MAIN INSTR.
SP+3
MAIN PROGRAM
SP+4
PC
$AD = JSR
SP+5
INDEXED, X
ff
SP+6
RTN
NEXT MAIN INSTR.
SP+7
SP+8
MAIN PROGRAM
SP+9
PC
$18 = PRE
INDEXED, Y
$AD = JSR
RTN
ff
NEXT MAIN INSTR.
MAIN PROGRAM
PC
$BD = PRE
hh
INDEXED, Y
RTN
ll
NEXT MAIN INSTR.
JMP, JUMP
MAIN PROGRAM
PC
$6E = JMP
ff
INDEXED, X
X + ff
NEXT MAIN INSTR.
MAIN PROGRAM
PC
$18 = PRE
$6E = JMP
ff
INDEXED, Y
X + ff
NEXT MAIN INSTR.
MAIN PROGRAM
PC
$7E = JMP
hh
ll
EXTENDED
hh ll
NEXT MAIN INSTR.
Figure 3-2 Stacking Operations
TECHNICAL DATA
For More Information On This Product,
WAI, WAIT FOR INTERRUPT
STACK
7
0
INTERRUPT ROUTINE
PC
$3E = WAI
CCR
ACCB
ACCA
IX
H
IX
L
IY
H
IY
L
RTN
H
RTN
L
SWI, SOFTWARE INTERRUPT
MAIN PROGRAM
PC
$3F = SWI
WAI, WAIT FOR INTERRUPT
MAIN PROGRAM
PC
$3E = WAI
BSR, BRANCH TO SUBROUTINE
MAIN PROGRAM
PC
$8D = BSR
RTS, RETURN FROM
SUBROUTINE
MAIN PROGRAM
PC
$39 = RTS
LEGEND:
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
BE EXECUTED UPON RETURN FROM SUBROUTINE
RTN
= MOST SIGNIFICANT BYTE OF RETURN ADDRESS
H
RTN
= LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
L
= STACK POINTER POSITION AFTER OPERATION IS COMPLETE
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
TO BE $00)
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (256) IS ADDED TO INDEX
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
STACK
7
0
SP
SP+1
CCR
SP+2
ACCB
SP+3
ACCA
SP+4
IX
H
SP+5
IX
L
SP+6
IY
H
SP+7
IY
L
SP+8
RTN
H
RTN
SP+9
L
STACK
7
0
SP–9
SP–8
CCR
SP–7
ACCB
SP–6
ACCA
SP–5
IX
H
SP–4
IX
L
SP–3
IY
H
SP–2
IY
L
SP–1
RTN
H
RTN
SP
L
STACK
7
0
SP–2
SP–1
RTN
H
SP
RTN
L
STACK
7
0
SP
SP+1
RTN
H
SP+2
RTN
L
HC11 STACK OPERATIONS
3-3