IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
Table 4-1 Register and Control Bit Assignments (Continued)
Bit 7
6
$002B
TCLR
0
SCP1
$002C
R8
T8
$002D
TIE
TCIE
RIE
$002E
TDRE
TC
RDRF
$002F
R7/T7
R6/T6
R5/T5
$0030
to
$0038
$0039
0
0
IRQE
$003A
Bit 7
6
$003B
$003C
RBOOT
SMOD
MDA
$003D
RAM3
RAM2
RAM1
$003E
TILOP
0
OCCR
$003F
0
0
The bootloader program is contained in the 192-byte bootstrap ROM. This ROM,
which appears as internal memory space at locations $BF40–$BFFF, is enabled only
if the MCU is reset in special bootstrap mode.
Memory locations are the same for expanded multiplexed and single-chip modes, ex-
cept for ROM in expanded mode and the bootloader ROM in special bootstrap mode.
The on-board 192-byte RAM is initially located at $0040 after reset, but can be placed
at any other 4K boundary ($x040) by writing an appropriate value to the INIT register.
The 4 Kbyte ROM is located at $F000 through $FFFF in all modes except expanded
multiplexed, in which it is located at $7000. ROM can be located at $F000 in expanded
multiplexed by entering single-chip mode out of reset and setting the MDA bit in the
HPRIO register to 1, thereby entering expanded mode from internal ROM. Disable
ROM by clearing the ROMON bit in the CONFIG register.
Hardware priority is built into RAM and I/O remapping. Registers and RAM have prior-
ity over ROM. In the event of conflicts, the higher priority resource takes precedence.
The 192 bytes of fully static RAM store instructions, variables, and temporary data.
The direct addressing mode can access RAM locations using a one-byte address op-
erand, saving program memory space and execution time, depending on the applica-
tion. RAM contents are preserved during periods of processor inactivity by two
methods, both of which reduce power consumption.
In the software-based STOP mode, the clocks are stopped while V
MCU. Because power supply current is directly related to operating frequency in
CMOS integrated circuits, only a very small amount of leakage exists when the clocks
are stopped.
OPERATING MODES AND ON-CHIP MEMORY
TECHNICAL DATA
For More Information On This Product,
5
4
3
2
SCP0
RCKB
SCR2
0
M
WAKE
0
ILIE
TE
RE
IDLE
OR
NF
R4/T4
R3/T3
R2/T2
DLY
CME
0
5
4
3
2
IRVNE
PSEL3
PSEL2
RAM0
REG3
REG2
CBYP
DISR
FCM
0
0
0
NOCOP
Go to: www.freescale.com
1
Bit 0
SCR1
SCR0
BAUD
0
0
SCCR1
RWU
SBK
SCCR2
FE
0
SCSR
R1/T1
R0/T0
SCDR
Reserved
Reserved
CR1
CR0
OPTION
1
Bit 0
COPRST
Reserved
PSEL1
PSEL0
HPRIO
REG1
REG0
INIT
FCOP
0
TEST1
ROMON
0
CONFIG
powers the
DD
4-5