MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 100

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Not implemented
9.4.2 Pulse Accumulator Control Register
DDRA7 — Data Direction Control for Port A Bit 7
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
DDRA3 — Data Direction Register for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5
9-14
TFLG2 — Timer Interrupt Flag 2
PACTL — Pulse Accumulator Control
RESET:
RESET:
Clear flags by writing a one to the corresponding bit position(s).
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Always read zero
Bits RTR[1:0] of this register select the rate for the real-time interrupt system. Bit
DDRA3 determines whether Port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Refer to SECTION 6 PARALLEL I/O.
Refer to 9.2 Input Capture.
DDRA7
Bit 7
TOF
Bit 7
0
0
PAEN
RTIF
Freescale Semiconductor, Inc.
6
0
6
0
For More Information On This Product,
PAMOD
PAOVF
Go to: www.freescale.com
5
0
5
0
TIMING SYSTEM
PEDGE
PAIF
4
0
4
0
DDRA3
3
0
0
3
0
I4/O5
2
0
0
2
0
RTR1
TECHNICAL DATA
1
0
0
1
0
$0025
$0026
RTR0
Bit 0
Bit 0
0
0
0