IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
TFLG2 — Timer Interrupt Flag 2
Bit 7
6
TOF
RTIF
RESET:
0
0
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.6 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.6 Pulse Accumulator.
Bits [3:0] — Not implemented
Always read zero
9.4.2 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the real-time interrupt system. Bit
DDRA3 determines whether Port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
PACTL — Pulse Accumulator Control
Bit 7
6
DDRA7
PAEN
RESET:
0
0
DDRA7 — Data Direction Control for Port A Bit 7
Refer to 9.6 Pulse Accumulator.
PAEN — Pulse Accumulator System Enable
Refer to 9.6 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode
Refer to 9.6 Pulse Accumulator.
PEDGE — Pulse Accumulator Edge Control
Refer to 9.6 Pulse Accumulator.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to SECTION 6 PARALLEL I/O.
I4/O5 — Input Capture 4/Output Compare 5
Refer to 9.2 Input Capture.
9-14
For More Information On This Product,
5
4
3
PAOVF
PAIF
0
0
0
0
5
4
3
PAMOD
PEDGE
DDRA3
0
0
0
TIMING SYSTEM
Go to: www.freescale.com
$0025
2
1
Bit 0
0
0
0
0
0
0
$0026
2
1
Bit 0
I4/O5
RTR1
RTR0
0
0
0
TECHNICAL DATA