MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 51

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Freescale Semiconductor, Inc.
The maskable interrupt sources have the following priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system
Any one of these interrupts can be assigned the highest maskable interrupt priority by
writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the
priority arrangement remains the same. An interrupt that is assigned highest priority is
still subject to global masking by the I bit in the CCR, or by any associated local bits.
Interrupt vectors are not affected by priority assignment. To avoid race conditions,
HPRIO can be written only while I-bit interrupts are inhibited.
5.3.1 Highest Priority Interrupt and Miscellaneous Register
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
Bit 7
6
RBOOT
SMOD
RESET:
The values of the RBOOT, SMOD, IRVNE, and MDA reset bits depend on the mode
during initialization. Refer to Table 5-3.
RBOOT — Read Bootstrap ROM
Has meaning only when the SMOD bit is a one (special bootstrap mode or special test
mode). At all other times this bit is clear and cannot be written. Refer to SECTION 4
OPERATING MODES AND ON-CHIP MEMORY for more information.
SMOD — Special Mode Select
This bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer to
SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information.
MDA — Mode Select A
The mode select A bit reflects the status of the MODA input pin at the rising edge of
reset. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more
information.
IRVNE — Internal Read Visibility Enable/Not E
TECHNICAL DATA
For More Information On This Product,
5
4
3
MDA
IRVNE
PSEL3
0
RESETS AND INTERRUPTS
Go to: www.freescale.com
$003C
2
1
Bit 0
PSEL2
PSEL1
PSEL0
1
0
1
5-7

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