IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
PR[1:0] — Timer Prescaler Select
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0]
can only be written once, and the write must be within 64 cycles after reset. Refer to
Table 9-1 for specific timing values.
9.3.10 Timer Interrupt Flag 2 Register
Bits in this register indicate when certain timer system events have occurred. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to
operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds
to a bit in TMSK2 in the same position.
TFLG2 — Timer Interrupt Flag 2
Bit 7
6
TOF
RTIF
RESET:
0
0
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Refer to 9.4 Real-Time Interrupt.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.6 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.6 Pulse Accumulator.
Bits [3:0]— Not implemented
Always read zero
9.4 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic
rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumu-
lator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt
capability. The four different rates available are a product of the MCU oscillator fre-
quency and the value of bits RTR[1:0]. Refer to the following table, which shows the
periodic real-time interrupt rates.
9-12
For More Information On This Product,
PR[1:0]
Prescaler
0 0
1
0 1
4
1 0
8
1 1
16
5
4
3
PAOVF
PAIF
0
0
0
0
TIMING SYSTEM
Go to: www.freescale.com
$0025
2
1
Bit 0
0
0
0
0
0
0
TECHNICAL DATA