MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 47

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
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OPTION — System Configuration Options
5.1.5 Option Register
Bits [7:6] and 2 — Not implemented
IRQE — Configure IRQ for Edge Sensitive Only Operation
DLY — Enable Oscillator Startup Delay
CME — Clock Monitor Enable
CR[1:0] — COP Timer Rate Select
TECHNICAL DATA
RESET:
Semiconductor wafer processing causes variations of the RC time-out values between
individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor
error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using
the clock monitor function when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock
monitor is enabled. Because the STOP function causes the clocks to be halted, the
clock monitor function generates a reset sequence if it is enabled at the time the STOP
mode was initiated. Before executing a STOP instruction, clear the CME bit in the OP-
TION register to zero to disable the clock monitor. After recovery from STOP, set the
CME bit to logic one to enable the clock monitor.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
Always read zero
This bit can be written only once during the first 64 E-clock cycles after reset in normal
modes.
This bit is set during reset and can be written only once during the first 64 E-clock cy-
cles after reset in normal modes. If an external clock source rather than a crystal is
used, the stabilization delay can be inhibited because the clock source is assumed to
be stable.
This control bit can be read or written at any time and controls whether or not the in-
ternal clock monitor circuit triggers a reset sequence when the system clock is slow or
absent. When it is clear, the clock monitor circuit is disabled. When it is set, the clock
monitor circuit is enabled. Reset clears the CME bit.
These control bits determine a scaling factor for the watchdog timer.
0 = Low level recognition
1 = Falling edge recognition
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
Bit 7
0
0
Freescale Semiconductor, Inc.
6
0
0
For More Information On This Product,
IRQE*
RESETS AND INTERRUPTS
Go to: www.freescale.com
5
0
DLY*
4
1
CME
3
0
2
0
0
CR1*
1
0
$0039
CR0*
Bit 0
0
5-3

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