IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
5.1.6 CONFIG Register
CONFIG — Configuration Control Register
Bit 7
6
0
0
RESET:
0
0
Bits [7:4] and 0 — Not implemented
Always read zero
NOCOP — COP System Disable
This bit is cleared out of reset in normal modes, enabling the COP system. It is set out
of reset in special modes. NOCOP is writable once in normal modes and at any time
in special modes.
0 = The COP system is enabled as the MCU comes out of reset.
1 = The COP system is disabled and does not generate system resets.
ROMON — Enable On-Chip ROM
Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.
5.2 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
reset vector can be fetched from any of six possible locations. Refer to Table 5-2.
Table 5-2 Reset Cause, Reset Vector, and Operating Mode
Cause of Reset
POR or RESET Pin
Clock Monitor Failure
COP Watchdog Time-out
These initial states then control on-chip peripheral systems to force them to known
startup states, as follows:
5.2.1 CPU
After reset, the CPU fetches the restart vector from the appropriate address during the
first three cycles, and begins executing instructions. The stack pointer and other CPU
registers are indeterminate immediately after reset; however, the X and I interrupt
mask bits in the condition code register (CCR) are set to mask any interrupt requests.
Also, the S bit in the CCR is set to inhibit the STOP mode.
5.2.2 Memory Map
After reset, the INIT register is initialized to $00, putting the 192 bytes of RAM at loca-
tions $0040 through $00FF, and the control registers at locations $0000 through
$003F.
5-4
For More Information On This Product,
5
4
3
0
0
0
NOCOP
0
0
0
Normal Mode Vector
$FFFE, FFFF
$FFFC, FFFD
$FFFA, FFFB
RESETS AND INTERRUPTS
Go to: www.freescale.com
$003F
2
1
Bit 0
ROMON
0
0
Special Test or Bootstrap
$BFFE, BFFF
$BFFC, $BFFD
$BFFA, BFFB
TECHNICAL DATA