IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
RTR[1:0]
E = 1 MHz
0 0
2.731 ms
0 1
5.461 ms
1 0
10.923 ms
1 1
21.845 ms
The clock source for the RTI function is a free-running clock that cannot be stopped or
interrupted except by reset. This clock causes the time between successive RTI time-
outs to be a constant that is independent of the software latencies associated with flag
clearing and service. For this reason, an RTI period starts from the previous time-out,
not from when RTIF is cleared.
Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire real-time interrupt period elapses before
the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and PACTL regis-
ters.
9.4.1 Timer Interrupt Mask 2 Register
This register contains the real-time interrupt enable bits.
TMSK2 — Timer Interrupt Mask 2
Bit 7
6
TOI
RTII
RESET:
0
0
TOI — Timer Overflow Interrupt Enable
Refer to 9.3 Output Compare.
RTII — Real-time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one
PAOVI — Pulse Accumulator Overflow Interrupt Enable
Refer to 9.6 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge
Refer to 9.6 Pulse Accumulator.
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
9.4.1 Timer Interrupt Flag 2 Register
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
TECHNICAL DATA
For More Information On This Product,
E = 2 MHz
E = 3 MHz
4.096 ms
8.192 ms
8.192 ms
16.384 ms
16.384 ms
32.768 ms
32.768 ms
65.536 ms
5
4
3
PAOVI
PAII
0
0
0
0
NOTE
TIMING SYSTEM
Go to: www.freescale.com
E = X MHz
13
(E/2
)
14
(E/2
)
15
(E/2
)
16
(E/2
)
$0024
2
1
Bit 0
0
PR1
PR0
0
0
0
9-13