IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
Page 36/124

Download datasheet (7Mb)Embed
PrevNext
Freescale Semiconductor, Inc.
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
AS
R/W
E
MCU
Figure 4-1 Address/Data Demultiplexing
4.1.3 Special Test Mode
Special test, a variation of the expanded multiplexed mode, is primarily used during
Motorola's internal production testing; however, it is accessible for programming the
CONFIG register, and supporting emulation and debugging during development.
4.1.4 Bootstrap Mode
When the MCU is reset in special bootstrap mode, a small amount of on-chip ROM is
enabled at address $BF00–$BFFF. The ROM contains a bootloader program and a
special set of interrupt and reset vectors. The MCU fetches the reset vector, then ex-
ecutes the bootloader.
For normal use of the bootloader program, send $FF to the SCI receiver at either E
clock 16, or E clock 104 (1200 baud for E clock equals 2 MHz). Then download up
to 192 bytes of program data, which is put into RAM starting at $0040. These charac-
ters are echoed through the transmitter. When loading is complete, the program jumps
to location $0040 and begins executing the code. The bootloader program ends the
download after 192 bytes, or when the received data line is idle for at least four char-
acter times. Use of an external pullup resistor is required when using the SCI transmit-
ter pin because port D pins are configured for wired-OR operation by the bootloader.
In bootstrap mode, the interrupt vectors are directed to RAM. This allows the use of
interrupts through a jump table. Refer to Freescale application note AN1060,
MC68HC11 Bootstrap Mode.
OPERATING MODES AND ON-CHIP MEMORY
4-2
For More Information On This Product,
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
HC373
Q1
ADDR7
D1
Q2
ADDR6
D2
ADDR5
D3
Q3
Q4
ADDR4
D4
ADDR3
D5
Q5
ADDR2
D6
Q6
Q7
ADDR1
D7
ADDR0
D8
Q8
LE
OE
WE
OE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Go to: www.freescale.com
ADDR/DATA DEMUX
TECHNICAL DATA