IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
Num
Characteristic
Frequency of Operation (E-Clock
Frequency)
1
Cycle Time
2
Pulse Width, E Low
PW
= 1/2 t
- 23ns
EL
cyc
3
Pulse Width, E High
PW
= 1/2 t
- 28 ns
EH
cyc
4A
E and AS Rise Time
4B
E and AS Fall Time
9
Address Hold Time
t
= 1/8 t
- 29.5 ns
AH
cyc
12
Non-Muxed Address Valid Time to E Rise
t
= PW
- (t
+ 80 ns)
AV
EL
ASD
17
Read Data Setup Time
18
Read Data Hold Time (Max = t
MAD
19
Write Data Delay Time
t
= 1/8 t
+ 65.5 ns
DDW
cyc
21
Write Data Hold Time
t
= 1/8 t
- 30 ns
DHW
cyc
22
Muxed Address Valid Time to E Rise
t
= PW
(t
+ 90 ns) (Note 1a)
AVM
EL -
ASD
24
Muxed Address Valid Time to AS Fall
t
= PW
- 70 ns
ASL
ASH
25
Muxed Address Hold Time
t
= 1/8 t
- 30 ns
AHL
cyc
26
Delay Time, E to AS Rise
t
= 1/8 t
- 5 ns
ASD
cyc
27
Pulse Width, AS High
PW
= 1/4 t
- 30 ns
ASH
cyc
28
Delay Time, AS to E Rise
t
= 1/8 t
- 5 ns
ASED
cyc
29
MPU Address Access Time
t
= t
– (PW
– t
) – t
ACCA
cyc
EL
AVM
35
MPU Access Time
t
= PW
- t
ACCE
EH
DSR
36
Muxed Address Delay
(Previous Cycle MPU Read)
t
= t
+ 30 ns(Note 1a)
MAD
ASD
NOTES:
1. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock
duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following
expressions in place of 1/8 t
cyc
(a) (1-DC)
1/4 t
cyc
(b) DC
1/4 t
cyc
Where:
DC is the decimal value of duty cycle percentage (high time).
2. All timing is shown with respect to 20% V
TECHNICAL DATA
For More Information On This Product,
Table A-6 Expansion Bus Timing
Symbol
1.0 MHz
Min
Max
f
dc
1.0
o
t
1000
cyc
PW
477
EL
PW
472
EH
t
20
r
t
20
f
t
95.5
AH
(Note 1a)
t
281.5
AV
(Note 1a)
t
30
DSR
)
t
0
145.5
DHR
t
190.5
DDW
(Note 1a)
t
95.5
DHW
(Note 1a)
t
271.5
AVM
t
151
ASL
t
95.5
AHL
(Note 1b)
t
115.5
ASD
(Note 1a)
PW
221
ASH
t
115.5
ASED
(Note 1b)
(Note 1a)
t
744.5
ACCA
–t
DSR
f
t
442
ACCE
t
145.5
MAD
in the above formulas, where applicable:
and 70% V
, unless otherwise noted.
DD
DD
ELECTRICAL CHARACTERISTICS
Go to: www.freescale.com
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
dc
2.0
dc
3.0
MHz
500
333
ns
227
146
ns
222
141
ns
20
20
ns
20
15
ns
33
26
ns
94
54
ns
30
30
ns
0
83
0
51
ns
128
71
ns
33
26
ns
84
54
ns
26
13
ns
33
31
ns
53
31
ns
96
63
ns
53
31
ns
307
196
ns
192
111
ns
83
51
ns
A-9