MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 85
Manufacturer Part Number
IC MCU 8BIT 3MHZ 52-PLCC
Specifications of MC68HC11E0CFNE3
Number Of I /o
Program Memory Type
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
No. Of I/o's
Ram Memory Size
No. Of Timers
Embedded Interface Type
Digital Ic Case Style
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
Lead Free Status / Rohs Status
SPSR — Serial Peripheral Status Register
SPDR — SPI Data Register
8.5.2 Serial Peripheral Status
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision
Bit 5 — Not implemented
MODF — Mode Fault
Bits [3:0] — Not implemented
8.5.3 Serial Peripheral Data I/O
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless
SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) fol-
lowed by an access of SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.
Always reads zero
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer
to 8.3.4 Slave Select and 8.4 SPI System Errors.
Always read zero
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
SPI is double buffered in and single buffered out.
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL PERIPHERAL INTERFACE
Go to: www.freescale.com