IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
8.5.2 Serial Peripheral Status
SPSR — Serial Peripheral Status Register
Bit 7
6
SPIF
WCOL
RESET:
0
0
SPIF — SPI Transfer Complete Flag
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless
SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited.
WCOL — Write Collision
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) fol-
lowed by an access of SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.
0 = No write collision
1 = Write collision
Bit 5 — Not implemented
Always reads zero
MODF — Mode Fault
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer
to 8.3.4 Slave Select and 8.4 SPI System Errors.
0 = No mode fault
1 = Mode fault
Bits [3:0] — Not implemented
Always read zero
8.5.3 Serial Peripheral Data I/O
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
SPDR — SPI Data Register
Bit 7
6
Bit 7
6
SPI is double buffered in and single buffered out.
SERIAL PERIPHERAL INTERFACE
TECHNICAL DATA
For More Information On This Product,
5
4
3
0
MODF
0
0
0
0
5
4
3
5
4
3
NOTE
Go to: www.freescale.com
$0029
2
1
Bit 0
0
0
0
0
0
0
$002A
2
1
Bit 0
2
1
Bit 0
8-7