IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
OC1M — Output Compare 1 Mask
Bit 7
6
OC1M7
OC1M6
RESET:
0
0
OC1M7–OC1M3 — Output Compare Masks
0 = OC1 is disabled
1 = OC1 is enabled to control the corresponding pin of port A
Bits [2:0] — Not implemented; always read zero
Set bit(s) to enable OC1 to control corresponding pin(s) of port A.
9.3.4 Output Compare 1 Data Register
Use this register with OC1 to specify the data that is to be stored on the affected pin
of port A after a successful OC1 compare. When a successful OC1 compare occurs,
a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in
OC1M.
OC1D — Output Compare 1 Data
Bit 7
6
OC1D7
OC1D6
RESET:
0
0
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] — Not implemented; always read zero
9.3.5 Timer Counter Register
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A
full counter read addresses the most significant byte (MSB) first. A read of this address
causes the least significant byte (LSB) to be latched into a buffer for the next CPU cy-
cle so that a double-byte read returns the full 16-bit state of the counter at the time of
the MSB read cycle.
TCNT — Timer Counter
$000E
Bit 15
14
13
$000F
Bit 7
6
5
TCNT resets to $0000.
In normal modes, TCNT is read-only.
9.3.6 Timer Control 1 Register
The bits of this register specify the action taken as a result of a successful OCx com-
pare.
TECHNICAL DATA
For More Information On This Product,
5
4
3
OC1M5
OC1M4
OC1M3
0
0
0
5
4
3
OC1D5
OC1D4
OC1D3
0
0
0
12
11
10
9
4
3
2
1
TIMING SYSTEM
Go to: www.freescale.com
$000C
2
1
Bit 0
0
0
0
0
0
0
$000D
2
1
Bit 0
0
0
0
0
0
0
$000E, $000F
Bit 8
TCNT (High)
Bit 0
TCNT (Low)
9-9