MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 64

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
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DDRB — Data Direction Register for Port B
PORTC — Port C Data
DDRC — Data Direction Register for Port C
DDB[7:0] — Data Direction for Port B
6.3 Port C
DDC[7:0] — Data Direction for Port C
6.4 Port D
6-2
RESET:
RESET:
RESET:
RESET:
or Boot:
or Test:
S. Chip
Expan.
Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul-
tiplexed mode, port C pins are configured as multiplexed address/data pins. During the
data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins controlled by the R/W signal.
The eight port D bits (PD[7:0]) can be used for general-purpose I/O, for the SCI and
SPI subsystems, or for bus data direction control. Port D can be read at any time. In-
puts return the sensed levels at the pin; outputs return the input level of the port D pin
drivers. If port D is written, the data is stored in an internal latch, and can be driven only
if port D is configured for general-purpose output. This port shares functions with the
on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow
on the bus in expanded and special test modes.
0 = Corresponding port B pin configured for input only
1 = Corresponding port B pin configured as output
0 = Input
1 = Output
ADDR7/
DATA7
DDC7
DDB7
Bit 7
Bit 7
PC7
PC7
Bit 7
0
0
ADDR6/
DATA6
DDC6
DDB6
PC6
PC6
Freescale Semiconductor, Inc.
6
0
6
6
0
Reset configures pins as multiplexed, low-order address/data I/O
For More Information On This Product,
ADDR5/
DATA5
DDC5
DDB5
PC5
PC5
Go to: www.freescale.com
5
0
5
5
0
Reset configures pins as HiZ inputs
PARALLEL I/O
ADDR4/
DATA4
DDC4
DDC4
PC4
PC4
4
0
4
4
0
ADDR3/
DATA3
DDC3
DDB3
PC3
PC3
3
0
3
3
0
ADDR2/
DATA2
DDC2
DDB2
PC2
PC2
2
0
2
2
0
ADDR1/
DATA1
DDC1
DDB1
PC1
PC1
TECHNICAL DATA
1
0
1
1
0
$0006
$0003
ADDR0/
$0007
DATA0
DDC0
DDB0
Bit 0
Bit 0
Bit 0
PC0
PC0
0
0

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