IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
DDRB — Data Direction Register for Port B
Bit 7
6
DDB7
DDB6
RESET:
0
0
DDB[7:0] — Data Direction for Port B
0 = Corresponding port B pin configured for input only
1 = Corresponding port B pin configured as output
6.3 Port C
Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul-
tiplexed mode, port C pins are configured as multiplexed address/data pins. During the
data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins controlled by the R/W signal.
PORTC — Port C Data
Bit 7
6
PC7
PC6
S. Chip
or Boot:
PC7
PC6
RESET:
Expan.
ADDR7/
ADDR6/
or Test:
DATA7
DATA6
RESET:
Reset configures pins as multiplexed, low-order address/data I/O
DDRC — Data Direction Register for Port C
Bit 7
6
DDC7
DDC6
RESET:
0
0
DDC[7:0] — Data Direction for Port C
0 = Input
1 = Output
6.4 Port D
The eight port D bits (PD[7:0]) can be used for general-purpose I/O, for the SCI and
SPI subsystems, or for bus data direction control. Port D can be read at any time. In-
puts return the sensed levels at the pin; outputs return the input level of the port D pin
drivers. If port D is written, the data is stored in an internal latch, and can be driven only
if port D is configured for general-purpose output. This port shares functions with the
on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow
on the bus in expanded and special test modes.
6-2
For More Information On This Product,
5
4
3
DDB5
DDC4
DDB3
0
0
0
5
4
3
PC5
PC4
PC3
PC5
PC4
PC3
Reset configures pins as HiZ inputs
ADDR5/
ADDR4/
ADDR3/
DATA5
DATA4
DATA3
5
4
3
DDC5
DDC4
DDC3
0
0
0
PARALLEL I/O
Go to: www.freescale.com
$0006
2
1
Bit 0
DDB2
DDB1
DDB0
0
0
0
$0003
2
1
Bit 0
PC2
PC1
PC0
PC2
PC1
PC0
ADDR2/
ADDR1/
ADDR0/
DATA2
DATA1
DATA0
$0007
2
1
Bit 0
DDC2
DDC1
DDC0
0
0
0
TECHNICAL DATA