MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 7

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Freescale Semiconductor, Inc.
LIST OF ILLUSTRATIONS
Figure
1-1
MC68HC11D3 Block Diagram ........................................................................ 1-2
2-1
Pin Assignments for 44-Pin PLCC ................................................................. 2-1
2-2
Pin Assignments for 40-Pin DIP ..................................................................... 2-2
2-3
External Reset Circuit ..................................................................................... 2-3
2-4
Common Crystal Connections ........................................................................ 2-3
2-5
External Oscillator Connections ..................................................................... 2-4
2-6
One Crystal Driving Two MCUs ..................................................................... 2-4
3-1
Programming Model ....................................................................................... 3-1
3-2
Stacking Operations ....................................................................................... 3-3
4-1
Address/Data Demultiplexing ......................................................................... 4-2
4-2
MC68HC11D3 Memory Map .......................................................................... 4-3
4-3
RAM Standby MODB/V
5-1
Processing Flow out of Reset (1 of 2) .......................................................... 5-12
5-2
Interrupt Priority Resolution (1 of 2) ............................................................. 5-14
5-3
Interrupt Source Resolution within SCI ........................................................ 5-16
7-1
SCI Transmitter Block Diagram ...................................................................... 7-2
7-2
SCI Receiver Block Diagram .......................................................................... 7-3
7-3
SCI Baud Rate Diagram ............................................................................... 7-10
7-4
Interrupt Source Resolution within SCI ........................................................ 7-12
8-1
SPI Block Diagram ......................................................................................... 8-2
8-2
SPI Transfer Format ....................................................................................... 8-3
9-1
Timer Clock Divider Chains ............................................................................ 9-2
9-2
Capture/Compare Block Diagram .................................................................. 9-4
9-3
Pulse Accumulator ....................................................................................... 9-16
A-1
Test Methods .................................................................................................. A-3
A-2
Timer Inputs ................................................................................................... A-4
A-3
POR and External Reset Timing Diagram ...................................................... A-5
A-4
STOP Recovery Timing Diagram ................................................................... A-6
A-5
WAIT Recovery Timing Diagram .................................................................... A-7
A-6
Port Write Timing Diagram ............................................................................. A-8
A-7
Port Read Timing Diagram ............................................................................. A-8
A-8
Multiplexed Expansion Bus Timing Diagram ................................................ A-10
A-9
SPI Master Timing (CPHA = 0) .................................................................... A-12
MC68HC11D3
TA
For More Information On This Product,
Title
Connections ...................................................... 4-6
STBY
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