IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
output port suitable for wired-OR operation. In wired-OR mode (a port C bit is at logic
level zero), it is actively driven low by the N-channel driver. When a port C bit is at logic
level one, the associated pin has high impedance, as neither the N- nor the P-channel
devices are active. It is customary to have an external pullup resistor on lines that are
driven by open-drain devices. Port C can only be configured for wired-OR operation
when the MCU is in single-chip mode. Refer to SECTION 6 PARALLEL I/O for addi-
tional information about port C functions.
2.10.4 Port D
Port D, an 8-bit, general-purpose I/O port has a data register (PORTD) and a data di-
rection register (DDRD). The eight port D bits (D[7:0]) can be used for general-purpose
I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)
subsystems, or for bus data direction control.
Port D can be read at any time and inputs return the sensed levels at the pin; whereas,
the outputs return the input level of the port D pin drivers. If PORTD is written, the data
is stored in an internal latch, and can be driven only if port D is configured for general-
purpose output. This port shares functions with the on-chip SCI and SPI subsystems,
while bits 6 and 7 control the direction of data flow on the bus in expanded and special
test modes.
Refer to SECTION 6 PARALLEL I/O.
2-8
For More Information On This Product,
PIN DESCRIPTIONS
Go to: www.freescale.com
TECHNICAL DATA