IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
TOC1–TOC4 — Timer Output Compare
$0016
Bit 15
14
$0017
Bit 7
6
$0018
Bit 15
14
$0019
Bit 7
6
$001A
Bit 15
14
$001B
Bit 7
6
$001C
Bit 15
14
$001D
Bit 7
6
All TOCx register pairs reset to ones ($FFFF)
TI4/O5 — Timer Input Capture 4/Output Compare 5
Refer to 9.2.3 Timer Input Capture 4/Output Compare 5 Register.
9.3.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5] correspond to the five
output compares. These bits are set for each output compare that is to be forced. The
action taken as a result of a forced compare is the same as if there were a match be-
tween the OCx register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their programmed pin
actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare because a normal compare that
occurs immediately before or after the force can result in an undesirable operation.
CFORC — Timer Compare Force
Bit 7
6
FOC1
FOC2
RESET:
0
0
FOC1–FOC5 — Write Ones to Force Compare(s)
0 = Not affected
1 = Output x action occurs
Bits [2:0] — Not implemented, always read zero
9.3.3 Output Compare Mask Registers
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1
compare. The bits of the OC1M register correspond to PA[7:3].
9-8
For More Information On This Product,
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FOC3
FOC4
FOC5
0
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TIMING SYSTEM
Go to: www.freescale.com
$0016–$001D
9
Bit 8
TOC1 (High)
1
Bit 0
TOC1 (Low)
9
Bit 8
TOC2 (High)
1
Bit 0
TOC2 (Low)
9
Bit 8
TOC3 (High)
1
Bit 0
TOC3 (Low)
9
Bit 8
TOC4 (High)
1
Bit 0
TOC4 (Low)
$001E, $001F
$000B
2
1
Bit 0
0
0
0
0
0
0
TECHNICAL DATA