MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 94

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
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CFORC — Timer Compare Force
TI4/O5 — Timer Input Capture 4/Output Compare 5
9.3.2 Timer Compare Force Register
FOC1–FOC5 — Write Ones to Force Compare(s)
Bits [2:0] — Not implemented, always read zero
9.3.3 Output Compare Mask Registers
9-8
TOC1–TOC4 — Timer Output Compare
RESET:
$001C
$001D
$001A
$001B
$0016
$0017
$0018
$0019
All TOCx register pairs reset to ones ($FFFF)
Refer to 9.2.3 Timer Input Capture 4/Output Compare 5 Register.
The CFORC register allows forced early compares. FOC[1:5] correspond to the five
output compares. These bits are set for each output compare that is to be forced. The
action taken as a result of a forced compare is the same as if there were a match be-
tween the OCx register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their programmed pin
actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare because a normal compare that
occurs immediately before or after the force can result in an undesirable operation.
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1
compare. The bits of the OC1M register correspond to PA[7:3].
0 = Not affected
1 = Output x action occurs
Bit 15
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
FOC1
Bit 7
0
14
14
14
14
6
6
6
6
FOC2
Freescale Semiconductor, Inc.
6
0
For More Information On This Product,
13
13
13
13
5
5
5
5
FOC3
Go to: www.freescale.com
5
0
TIMING SYSTEM
12
12
12
12
4
4
4
4
FOC4
4
0
11
11
11
11
3
3
3
3
FOC5
3
0
10
10
10
10
2
2
2
2
2
0
0
9
1
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
TECHNICAL DATA
$001E, $001F
$0016–$001D
1
0
0
TOC1 (High)
TOC2 (High)
TOC3 (High)
TOC4 (High)
TOC1 (Low)
TOC2 (Low)
TOC3 (Low)
TOC4 (Low)
$000B
Bit 0
0
0

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