MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 101

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

RTR[1:0] — RTI Interrupt Rate Select
9.5 Computer Operating Properly Watchdog Function
9.6 Pulse Accumulator
TECHNICAL DATA
These two bits determine the rate at which the RTI system requests interrupts. The
RTI system is driven by an E divided by 2
dependent of the timer prescaler. These two control bits select an additional division
factor.
The clocking chain for the COP function, tapped off of the main timer divider chain, is
only superficially related to the main timer system. The CR[1:0] bits in the OPTION
register and the NOCOP bit in the CONFIG register determine the status of the COP
function. Refer to SECTION 5 RESETS AND INTERRUPTS for a more detailed dis-
cussion of the COP function.
The MC68HC11D3 has an 8-bit counter that can be configured to operate either as a
simple event counter, or for gated time accumulation, depending on the state of the
PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Fig-
ure 9-3.
In the event counting mode, the 8-bit counter is clocked to increasing values by an ex-
ternal pin. The maximum clocking rate for the external event counting mode is the E
clock divided by two. In gated time accumulation mode, a free-running E-clock
signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to
Table 9-3. The pulse accumulator counter can be read or written at any time.
RTR[1:0]
0 0
0 1
1 0
1 1
E = 1 MHz
10.923 ms
21.845 ms
Freescale Semiconductor, Inc.
2.731 ms
5.461 ms
For More Information On This Product,
Go to: www.freescale.com
TIMING SYSTEM
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
13
rate clock that is compensated so it is in-
E = 3 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
E = X MHz
(E/2
(E/2
(E/2
(E/2
13
14
15
16
)
)
)
)
9-15
64