IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
RTR[1:0] — RTI Interrupt Rate Select
These two bits determine the rate at which the RTI system requests interrupts. The
RTI system is driven by an E divided by 2
dependent of the timer prescaler. These two control bits select an additional division
factor.
RTR[1:0]
E = 1 MHz
0 0
2.731 ms
0 1
5.461 ms
1 0
10.923 ms
1 1
21.845 ms
9.5 Computer Operating Properly Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is
only superficially related to the main timer system. The CR[1:0] bits in the OPTION
register and the NOCOP bit in the CONFIG register determine the status of the COP
function. Refer to SECTION 5 RESETS AND INTERRUPTS for a more detailed dis-
cussion of the COP function.
9.6 Pulse Accumulator
The MC68HC11D3 has an 8-bit counter that can be configured to operate either as a
simple event counter, or for gated time accumulation, depending on the state of the
PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Fig-
ure 9-3.
In the event counting mode, the 8-bit counter is clocked to increasing values by an ex-
ternal pin. The maximum clocking rate for the external event counting mode is the E
clock divided by two. In gated time accumulation mode, a free-running E-clock
signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to
Table 9-3. The pulse accumulator counter can be read or written at any time.
TECHNICAL DATA
For More Information On This Product,
13
rate clock that is compensated so it is in-
E = 2 MHz
E = 3 MHz
4.096 ms
8.192 ms
8.192 ms
16.384 ms
16.384 ms
32.768 ms
32.768 ms
65.536 ms
TIMING SYSTEM
Go to: www.freescale.com
E = X MHz
13
(E/2
)
14
(E/2
)
15
(E/2
)
16
(E/2
)
64
9-15