IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
8.5.1 Serial Peripheral Control
SPCR — Serial Peripheral Control Register
Bit 7
6
SPIE
SPE
RESET:
0
0
SPIE — Serial Peripheral Interrupt Enable
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — Serial Peripheral System Enable
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode
DWOM affects all six port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of
the master device has a steady state low value. When CPOL is set, SCK idles high.
Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relation-
ship between master and slave. The CPHA bit selects one of two different clocking
protocols. Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.
SPR1 and SPR0 — SPI Clock Rate Selects
These two serial peripheral rate bits select one of four baud rates to be used as SCK
if the device is a master; however, they have no effect in the slave mode.
SPR[1:0]
0 0
0 1
1 0
1 1
SERIAL PERIPHERAL INTERFACE
8-6
For More Information On This Product,
5
4
3
DWOM
MSTR
CPOL
0
0
0
E Clock
Frequency at
Divide By
E = 2 MHz (Baud)
2
1.0 MHz
4
500 kHz
16
125 kHz
32
62.5 kHz
Go to: www.freescale.com
$0028
2
1
Bit 0
CPHA
SPR1
SPR0
1
U
U
TECHNICAL DATA