MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 26

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
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3.1.6.8 Stop Disable (S)
3.2 Data Types
3.3 Opcodes and Operands
3.4 Addressing Modes
3-6
terrupt occurred. The X interrupt mask bit is set only by hardware (or acknowledge). X
is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI,
where bit 6 of the value loaded into the CCR from the stack has been cleared). There
is no hardware action for clearing X.
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop condition. If the STOP instruction is encountered by
the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction, and
processing continues to the next instruction. S is set by reset —STOP disabled by de-
fault.
The M68HC11 CPU supports the following data types:
A byte is eight bits wide and can be accessed at any byte location. A word is composed
of two consecutive bytes with the most significant byte at the lower value address. Be-
cause the M68HC11 is an 8-bit CPU, there are no special requirements for alignment
of instructions or operands.
The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies
a particular instruction and associated addressing mode to the CPU. Several opcodes
are required to provide each instruction with a range of addressing capabilities. Only
256 opcodes would be available if the range of values were restricted to the number
able to be expressed in 8-bit binary numbers.
A four-page opcode map has been implemented to expand the number of instructions.
An additional byte, called a prebyte, directs the processor from page 0 of the opcode
map to one of the other three pages. As its name implies, the additional byte precedes
the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or
three operands. The operands contain information the CPU needs for executing the
instruction. Complete instructions can be from one to five bytes long.
Six addressing modes; immediate, direct, extended, indexed, inherent, and relative,
detailed in the following paragraphs, can be used to access memory. All modes except
inherent mode use an effective address. The effective address is the memory address
from which the argument is fetched or stored, or the address from which execution is
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
TECHNICAL DATA

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