IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
SECTION 9
TIMING SYSTEM
The M68HC11 timing system is composed of five clock divider chains. The main clock
divider chain includes a 16-bit free-running counter, which is driven by a programma-
ble prescaler. The main timer's programmable prescaler provides one of the four
clocking rates to drive the 16-bit counter. Two prescaler control bits select the prescale
rate.
The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off of this main
clocking chain drive circuitry that generates the slower clocks used by the pulse accu-
mulator, the real-time interrupt (RTI), and the computer operating properly (COP)
watchdog subsystems, also described in this section. Refer to Figure 9-1.
All main timer system activities are referenced to this free-running counter. The
counter begins incrementing from $0000 as the MCU comes out of reset, and contin-
ues to the maximum count, $FFFF. At the maximum count, the counter rolls over to
$0000, sets an overflow flag, and continues to increment. As long as the MCU is run-
ning in a normal operating mode, there is no way to reset, change, or interrupt the
counting. The capture/compare subsystem features three input capture channels, four
output compare channels, and one channel that can be selected to perform either in-
put capture or output compare. Each of the three input capture functions has its own
16-bit input capture register (time capture latch) and each of the output compare func-
tions has its own 16-bit compare register. All timer functions, including the timer over-
flow and RTI have their own interrupt controls and separate interrupt vectors.
The pulse accumulator contains an 8-bit counter and edge select logic. The pulse ac-
cumulator can operate in either event counting or gated time accumulation modes.
During event counting mode, the pulse accumulator's 8-bit counter increments when
a specified edge is detected on an input signal. During gated time accumulation mode,
an internal clock source increments the 8-bit counter while an input signal has a pre-
determined logic level.
RTI is a programmable periodic interrupt circuit that permits pacing the execution of
software routines by selecting one of four interrupt rates.
15
The COP watchdog clock input (E 2
) is tapped off of the free-running counter chain.
The COP automatically times out unless it is serviced within a specific time by a pro-
gram reset sequence. If the COP is allowed to time out, a reset is generated, which
drives the RESET pin low to reset the MCU and the external system. Refer to Table
9-1 for crystal related frequencies and periods.
TIMING SYSTEM
TECHNICAL DATA
9-1
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