IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 

Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
Table 3-2 Instruction Set (Sheet 2 of 7)
Mnemonic
Operation
Description
BCLR (opr)
Clear Bit(s)
M • (mm)
M
(msk)
BCS (rel)
Branch if Carry
? C = 1
Set
BEQ (rel)
Branch if =
? Z = 1
Zero
BGE (rel)
Branch if
? N
V = 0
Zero
BGT (rel)
Branch if >
? Z + (N
V) = 0
Zero
BHI (rel)
Branch if
? C + Z = 0
Higher
BHS (rel)
Branch if
? C = 0
Higher or
Same
BITA (opr)
Bit(s) Test A
A • M
with Memory
BITB (opr)
Bit(s) Test B
B • M
with Memory
BLE (rel)
Branch if
? Z + (N
V) = 1
Zero
BLO (rel)
Branch if
? C = 1
Lower
BLS (rel)
Branch if
? C + Z = 1
Lower or
Same
BLT (rel)
Branch if <
? N
V = 1
Zero
BMI (rel)
Branch if
? N = 1
Minus
BNE (rel)
Branch if not =
? Z = 0
Zero
BPL (rel)
Branch if Plus
? N = 0
BRA (rel)
Branch Always
? 1 = 1
BRCLR(opr)
Branch if
? M • mm = 0
(msk)
Bit(s) Clear
(rel)
BRN (rel)
Branch Never
? 1 = 0
BRSET(opr)
Branch if Bit(s)
? (M) • mm = 0
(msk)
Set
(rel)
BSET (opr)
Set Bit(s)
M + mm
M
(msk)
BSR (rel)
Branch to
See Figure 3–2
Subroutine
BVC (rel)
? V = 0
Branch if
Overflow Clear
BVS (rel)
Branch if
? V = 1
Overflow Set
CBA
Compare A to
A – B
B
CLC
Clear Carry Bit
0
C
CLI
Clear Interrupt
0
I
Mask
CLR (opr)
Clear Memory
0
M
Byte
TECHNICAL DATA
For More Information On This Product,
Addressing
Instruction
Mode
Opcode
Operand Cycles
DIR
15
dd mm
6
IND,X
1D
ff mm
7
IND,Y
18
1D
ff mm
8
REL
25
rr
3
REL
27
rr
3
REL
2C
rr
3
REL
2E
rr
3
REL
22
rr
3
REL
24
rr
3
2
A
IMM
85
ii
A
DIR
95
dd
3
A
EXT
B5
hh ll
4
A
IND,X
A5
ff
4
A
IND,Y
18
A5
ff
5
2
B
IMM
C5
ii
B
DIR
D5
dd
3
B
EXT
F5
hh ll
4
B
IND,X
E5
ff
4
B
IND,Y
18
E5
ff
5
REL
2F
rr
3
REL
25
rr
3
3
REL
23
rr
REL
2D
rr
3
REL
2B
rr
3
REL
26
rr
3
REL
2A
rr
3
REL
20
rr
3
DIR
13
dd mm rr
6
IND,X
1F
ff mm rr
7
IND,Y
18
1F
ff mm rr
8
REL
21
rr
3
DIR
12
dd mm rr
6
IND,X
1E
ff mm rr
7
IND,Y
18
1E
ff mm rr
8
DIR
14
dd mm
6
IND,X
1C
ff mm
7
IND,Y
18
1C
ff mm
8
REL
8D
rr
6
3
REL
28
rr
REL
29
rr
3
INH
11
2
INH
0C
2
INH
0E
2
EXT
7F
hh ll
6
IND,X
6F
ff
6
IND,Y
18
6F
ff
7
CENTRAL PROCESSING UNIT
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Condition Codes
S
X
H
I
N
Z
V
C
0
0
0
0
0
0
0
1
0
0
3-9