IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part NumberMC68HC11E0CFNE3
DescriptionIC MCU 8BIT 3MHZ 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC11E0CFNE3 datasheets
 


Specifications of MC68HC11E0CFNE3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory TypeROMlessRam Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCController Family/series68HC11
No. Of I/o's38Ram Memory Size512Byte
Cpu Speed3MHzNo. Of Timers1
Embedded Interface TypeSCI, SPIDigital Ic Case StyleLCC
Rohs CompliantYesProcessor SeriesHC11E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency3 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bit, 8 ChannelLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Program Memory Size-
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Freescale Semiconductor, Inc.
Table 5-4 Interrupt and Reset Vector Assignments
Vector Address
FFC0, C1 — FFD4, D5
Reserved
FFD6, D7
SCI Serial System
FFD8, D9
SPI Serial Transfer Complete
FFDA, DB
Pulse Accumulator Input Edge
FFDC, DD
Pulse Accumulator Overflow
FFDE, DF
Timer Overflow
FFE0, E1
Timer Input Capture 4/Output Compare 5
FFE2, E3
Timer Output Compare 4
FFE4, E5
Timer Output Compare 3
FFE6, E7
Timer Output Compare 2
FFE8, E9
Timer Output Compare 1
FFEA, EB
Timer Input Capture 3
FFEC, ED
Timer Input Capture 2
FFEE, EF
Timer Input Capture 1
FFF0, F1
Real Time Interrupt
FFF2, F3
IRQ (External Pin)
FFF4, F5
XIRQ Pin
FFF6, F7
Software Interrupt
FFF8, F9
Illegal Opcode Trap
FFFA, FB
COP Failure
FFFC, FD
Clock Monitor Fail
FFFE, FF
RESET
5.4.1 Interrupt Recognition and Register Stacking
An interrupt can be recognized at any time after it is enabled by its local mask, if any,
and by the global mask bit in the CCR. Once an interrupt source is recognized, the
CPU responds at the completion of the instruction being executed. Interrupt latency
varies according to the number of cycles required to complete the current instruction.
When the CPU begins to service an interrupt, the contents of the CPU registers are
pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,
the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The inter-
rupt vector for the highest priority pending source is fetched, and execution continues
at the address specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are pulled from the
stack in reverse order so that normal program execution can resume. Refer to SEC-
TION 3 CENTRAL PROCESSING UNIT for further information.
TECHNICAL DATA
For More Information On This Product,
Interrupt Source
SCI Transmit Complete
SCI Transmit Data Register Empty
SCI Idle Line Detect
SCI Receiver Overrun
SCI Receive Data Register Full
RESETS AND INTERRUPTS
Go to: www.freescale.com
CCR Mask
Local
Mask
I Bit
TCIE
TIE
ILIE
RIE
RIE
I Bit
SPIE
I Bit
PAII
I Bit
PAOVI
I Bit
TOI
I Bit
I4/O5I
I Bit
OC4I
I Bit
OC3I
I Bit
OC2I
I Bit
OC1I
I Bit
IC3I
I Bit
IC2I
I Bit
IC1I
I Bit
RTII
I Bit
None
X Bit
None
None
None
None
None
None
NOCOP
None
CME
None
None
5-9