MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 32

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

3-12
ORAA (opr)
ORAB (opr)
Mnemonic
ROR (opr)
NEG (opr)
ROL (opr)
RORA
RORB
LSRD
NEGA
NEGB
PSHA
PSHB
PSHX
PSHY
ROLA
ROLB
LSRB
PULA
PULB
PULX
PULY
NOP
MUL
RTS
SBA
RTI
Rotate Right A
Rotate Right B
Multiply 8 by 8
Right Double
Memory Byte
Rotate Left A
Rotate Left B
Complement
Complement
Complement
No operation
Logical Shift
Logical Shift
Accumulator
A (Inclusive)
Accumulator
Push A onto
Push B onto
Push X onto
Push Y onto
Rotate Right
B (Inclusive)
Pull X From
Return from
Return from
Pull A from
Pull B from
Pull Y from
Rotate Left
Operation
Subroutine
Subtract B
Stack (Lo
Stack (Lo
Stack (Hi
Stack (Hi
Interrupt
Right B
from A
Two’s
Two’s
Two’s
Stack
Stack
Stack
Stack
First)
First)
First)
First)
OR
OR
A
B
0
A
B
IX
IY
SP = SP + 1, A
SP = SP + 1, B
SP = SP + 2, IX
SP = SP + 2, IY
0
b7
See Figure 3–2
See Figure 3–2
No Operation
Description
Stk,SP = SP – 1 A
Stk,SP = SP – 1 B
0 – M
A + M
B + M
C b7
C b7
C b7
b7
b7
b7
A
Stk,SP = SP – 2
Stk,SP = SP – 2
A – B
b7
A
0 – A
0 – B
b0
Freescale Semiconductor, Inc.
Stk
Stk
Table 3-2 Instruction Set (Sheet 5 of 7)
B
b7
For More Information On This Product,
b0
b0
b0
B
b0
D
M
A
B
A
B
A
C
C
C
b0
b0
b0
b0
C
Stk A
Stk B
C
CENTRAL PROCESSING UNIT
B
A
B
A
A
A
A
A
B
B
B
B
B
A
B
A
B
Addressing
Go to: www.freescale.com
Mode
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
18
18
18
18
18
18
18
Opcode
54
04
3D
70
60
60
40
50
01
8A
9A
AA
AA
CA
DA
EA
EA
36
37
3C
3C
32
33
38
38
79
69
69
49
59
76
66
66
46
56
3B
39
10
BA
FA
Instruction
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ff
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dd
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ff
ff
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hh ll
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Operand Cycles
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12
2
3
6
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3
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H
Condition Codes
TECHNICAL DATA
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0
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Z
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