AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 11

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Mnemonic
POWER SUPPLY
VDDCORE
VDDIO
GND
INPUT (ADC) PORTS (CMOS/LVDS)
CLKA
CLKB
CLKC
CLKD
INA[0:15]
INB[0:15]
INC[0:15]
IND[0:15]
EXPA[0:2]
M
A
B
C
D
G
H
K
N
R
E
P
F
J
L
T
VDDCORE
CPUCLK
(SCLK)
EXPA1
EXPB0
INA14
INA12
INA11
CLKA
CLKB
IND0
INA5
INA4
INA2
GND
GND
GND
1
1
EXPD1
EXPC2
VDDIO
VDDIO
INA15
INA13
INB13
INA10
INC3
INA9
INA8
INA6
INB5
INA3
INA1
IRP
2
2
Type
Power
Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Bidirectional
EXPC1
EXPA0
EXPB1
RESET
MODE
INB15
INB12
INB10
MSB_
FIRST
IND4
INC2
INC0
INA7
INB4
INB2
INA0
3
3
R/W (WR,
CHIPID0
DS (RD,
FILTER
EXPD0
EXPC0
EXPB2
LVDS_
SRFS)
INB11
STFS)
RSET
EXT_
IND7
IND5
INC1
INB8
INB6
INB1
INB0
4
4
Pin No.
See Table 9
See Table 9
See Table 9
K1
L1
A6
A5
See Table 9
See Table 9
See Table 9
See Table 9
E3, C1, G5
CS (SCS)
CHIPID1
SMODE
EXPD2
EXPA2
INB14
CLKD
IND6
IND3
IND2
GND
INB9
INB7
INB3
GND
D7
5
5
= VDDCORE
(RDY, SDO)
VDDCORE
VDDCORE
VDDCORE
VDDCORE
CHIPID2
CHIPID3
DTACK
CLKC
IND8
INC5
INC4
IND1
GND
GND
D14
D8
6
6
Function
1.8 V Digital Core Supply.
3.3 V Digital I/O Supply.
Digital Core and I/O Ground.
Clock for Input Port A. Used to clock INA[15:0] and EXPA[2:0] data. Additionally, this clock
is used to drive internal circuitry and PLL clock multiplier.
Clock for Input Port B. Used to clock INB[15:0] and EXPB[2:0] data.
Clock for Input Port C. Used to clock INC[15:0] and EXPC[2:0] data.
Clock for Input Port D. Used to clock IND[15:0] and EXPD[2:0] data.
Input Port A (Parallel).
Input Port B (Parallel).
Input Port C (Parallel).
Input Port D (Parallel).
Exponent Bus Input Port A. Gain control output.
VDDIO
VDDIO
IND11
IND10
IND9
INC7
INC6
GND
GND
GND
GND
GND
D13
D12
D10
Figure 2. CSP_BGA Pin Configuration
D3
7
7
VDDCORE
Rev. A | Page 11 of 80
VDDIO
VDDIO
IND12
INC10
INC9
INC8
GND
GND
GND
GND
GND
D15
D11
D2
D9
8
8
VDDCORE
VDDIO
VDDIO
= VDDIO
IND13
INC13
INC12
INC11
GND
GND
GND
GND
GND
D5
D1
D4
D6
9
9
SYNC2
VDDIO
VDDIO
IND14
INC14
INC15
GND
GND
GND
GND
GND
TDI
10
A5
A4
A6
D0
10
VDDCORE
VDDCORE
VDDCORE
VDDCORE
A0 (SDI)
PBREQ
SYNC3
PBCH1
IND15
PC12
TMS
GND
GND
11
A2
A3
A7
11
PBACK
SYNC1
SYNC0
PACH2
TCLK
PC15
PC14
PBIQ
PA12
PC11
PB6
PB3
PA3
PC3
PC7
12
A1
12
= GROUND
PAGAIN
PCACK
PBCH0
TRST
PB14
PC10
PC13
PAIQ
PA15
TDO
PB4
PB0
PA7
PC2
PC5
PC9
13
13
PBGAIN
PAACK
PBCH2
PCCH1
PB8
PB9
PB5
PB7
PB2
PC0
PC1
PC4
PC6
PC8
PA5
PA9
14
14
PAREQ
PACH0
PCCH0
PCCH2
VDDIO
VDDIO
PB11
PB15
PB13
PA13
PCIQ
GND
PB1
PA1
PA4
PA8
15
15
VDDCORE
PCGAIN
PCREQ
PACH1
PCLK
AD6636
PB12
PB10
PA10
PA11
PA14
GND
GND
GND
PA0
PA2
PA6
16
16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T