AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 44

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
clipping level option provides a way to prevent truncating those
signals and still provide an AGC that attacks quickly and settles
to the desired output level. The signal path for this mode of
operation is shown with dotted lines in Figure 39; the operation
is similar to the desired signal level mode.
First, the data from the gain multiplier is truncated to a lower
resolution (4 bits, 5 bits, 6 bits, 7 bits, 8 bits, 10 bits, 12 bits, or
16 bits) as set by the AGC output word length word in the AGC
control register. An error term (for both I and Q) is generated
that is the difference between the signals before and after
truncation. This term is passed to the complex squared
magnitude block, for averaging and decimating the update
samples and taking their square root to find rms samples as in
desired signal level mode. In place of the request desired signal
level, a desired clipping level is subtracted, leaving an error term
to be processed by the second-order loop filter.
The rest of the loop operates the same way as the desired signal
level mode. This way, the truncation error is calculated and the
AGC loop operates to maintain a constant truncation error
level. The only register setting that is different from the desired
signal level mode settings is that the desired clipping level is
stored in the AGC desired level registers instead of in the
request signal level.
AGC Synchronization
When the AGC output is connected to a RAKE receiver, the
RAKE receiver can synchronize the average and update section
to update the average power for AGC error calculation and loop
filtering. This external sync signal synchronizes the AGC
changes to the RAKE receiver and makes sure that the AGC
gain word does not change over a symbol period, which,
therefore, provides a more accurate estimation. This synchro-
nization can be accomplished by setting the appropriate bits of
the AGC control register.
Sync Select Alternatives
The AGC can receive a sync as follows:
•
•
•
When the channel sync select bit of the AGC control register is
Logic 1, the AGC receives the SYNC signal used by the NCO of
the corresponding channel for the start. When this bit is
Logic 0, the pin sync defined by the 2-bit SYNC pin select word
in the AGC control register is used to provide the sync to the
AGC. Apart from these two methods, the AGC control register
also has a sync now bit that can be used to provide a sync to
the AGC by writing to this register through the microport or
serial port.
Channel sync: The sync signal is used to synchronize the
NCO of the channel under consideration.
Pin sync: Select one of the four SYNC pins.
Sync now bit: Through the AGC control register.
Rev. A | Page 44 of 80
Sync Process
Regardless of how a sync signal is received, the syncing process
is the same. When a sync is received, a start hold-off counter is
loaded with the 16-bit value in the AGC hold-off register, which
initiates the countdown. The countdown is based on the ADC
input clock. When the count reaches 1, a sync is initiated. When
a sync is initiated, the CIC decimation filter dumps the current
value to the square root, error estimation, and loop filter blocks.
After dumping the current value, it starts working toward the
next update value. Additionally on a sync, AGC can be
initialized if the initialize AGC on sync bit is set in the AGC
control register. During initialization, the CIC accumulator is
cleared and new values for CIC decimation, number of
averaging samples, CIC scale, signal gain, open-loop gains K
and K
registers. When the initialize on sync bit is cleared, these
parameters are not loaded from the registers.
This sync process is also initiated when a channel comes out of
sleep by using the start sync to the NCO. An additional feature
is the first sync only bit in the AGC control register. When this
bit is set, the first sync initiates the process only and the
remaining sync signals are ignored. This is useful when syncing
using a pin sync. A sync is required on the first pulse on this pin
only. These additional features make AGC synchronization
more flexible and applicable to varied circumstances.
PARALLEL PORT OUTPUT
The AD6636 incorporates three independent 16-bit parallel
ports for output data transfer. The three parallel output ports
share a common clock, PCLK. Each port consists of a 16-bit
data bus, a REQuest signal, an ACKnowledge signal, three
channel indicator pins, one I/Q indicator pin, one gain word
indicator pin, and a common shared PCLK pin. The parallel
ports can be configured to function in master or slave mode. By
default, the parallel ports are in slave mode on power-up.
Each parallel port can output data from any or all of the AGCs,
using the 1-bit enable bit for each AGC in the parallel port
control register. Even when the AGC is not required for a
certain channel, the AGC can be bypassed, but the data is still
received from the bypassed AGC. The parallel port
functionality is programmable through the two parallel port
control registers.
Each parallel port can be programmed individually to operate
in either interleaved I/Q mode or parallel I/Q mode. The mode
is selected using a 1-bit data format bit in the parallel port
control register. In both modes, the AGC gain word output can
be enabled using a 1-bit append gain bit in the parallel port
control register for individual output ports. There are six enable
bits per output port, one for each AGC in the corresponding
parallel port.
2
, and pole parameter P are loaded from their respective
1