AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 69

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

<3>: NCO Bypass Bit. When this bit is set, the NCO is bypassed
and shuts down for power savings. When a NCO frequency of
dc or 0 Hz is required, this bit can be used for power savings.
When this bit is cleared, the NCO operates as programmed.
<2>: Clear NCO Accumulator Bit. When this bit is set, the clear
NCO accumulator bit synchronously clears the phase accumu-
lator on all frequency hops in this channel. When this bit is
cleared, the accumulator is not cleared and phase continuous
hops are implemented.
<1>: Phase Dither Enable Bit. When this bit is set, phase
dithering in the NCO is enabled. When this bit is cleared, phase
dithering is disabled.
<0>: Amplitude Dither Enable Bit. When this bit is set,
amplitude dithering in the NCO is enabled. When this bit is
cleared, amplitude dithering is disabled.
Channel Start Hold-Off Counter <15:0>
When a start synchronization (software or hardware) occurs on
the channel, the value in this register is loaded into a down-
counter. When the counter has finished counting down to 0, the
channel operation is started.
NCO Frequency Hop Hold-Off Counter <15:0>
When a hop sync occurs, a counter is loaded with the NCO
frequency hold-off register value. The 16-bit counter starts
counting down. When it reaches 0, the new frequency value in
the shadow register is written to the NCO frequency register
(see the Numerically Controlled Oscillator (NCO) section).
NCO Frequency <31:0>
The value in this register is used to program the NCO tuning
frequency. The value to be programmed is given by
where:
NCO_FREQUENCY is the desired NCO tuning frequency.
CLK is the ADC clock rate.
The value given by the equation should be loaded into the
register in binary format.
NCO Phase Offset <15:0>
The value in the register is loaded into the phase accumulator of
the NCO block every time a start sync or hop sync is received
by the channel. This allows individual channels to be started
with a known nonzero phase. If Bit <2> of the NCO control
register (clear phase accumulator on hop) is cleared, the NCO
phase offset is not loaded on a hop sync,. This NCO offset
register value is interpreted as a 16-bit unsigned integer. A
NCO Frequency Register =
NCO _
FREQUENCY
CLK
× 2
32
Rev. A | Page 69 of 80
0x0000 in this register corresponds to a 0 radian offset, and a
0xFFFF corresponds to an offset of 2π (1 − 1/(2
CIC Bypass <0>
When this bit is set, the entire CIC filter is bypassed. The
output of CIC filter is driven straight from the input without
any change. When this bit is cleared, the CIC filter operates in
normal mode as programmed. Writing Logic 1 to this bit
disables both the CIC decimation operation and the CIC
scaling operation.
CIC Decimation <4:0>
This 5-bit word specifies the CIC filter decimation value minus
1. A value of 0x00 is a decimation of 1 (bypass), and 0x1F is a
decimation of 32. Writing a value of 0 in this register bypasses
CIC filtering but does not bypass the CIC scaling operation.
CIC Scale Factor <4:0>
This 5-bit word specifies the CIC filter scale factor used to
compensate for the gain provided by the CIC filter. The
recommended value is given by
where:
M
in the CIC decimation register).
The ceil operation gives the closest integer greater than or equal
to the argument.
The valid range for this register is decimal 0 to 20.
FIR-HB Control <3:0>
<3>: FIR1 Enable Bit. When this bit is set, the FIR1 fixed-
coefficient filter is enabled. When cleared, FIR1 is bypassed.
<2>: HB1 Enable Bit. When this bit is set, the HB1 half-band
filter is enabled. When cleared, HB1 is bypassed.
<1>: FIR2 Enable Bit. When this bit is set, the FIR2 fixed-
coefficient filter is enabled. When cleared, FIR2 is bypassed.
<0>: HB2 Enable bit. When this bit is set, the HB2 half-band
filter is enabled. When cleared, HB2 is bypassed.
CIC
CIC Scale Register = ceil(5 × log
is the decimation rate of the CIC (one more than the value
2
(M
CIC
)) − 5
16
)) radians.
AD6636