AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 36

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
5.
6.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be written first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes to the
coefficient memory register.
CHANNEL RAM COEFFICIENT FILTER (CRCF)
Following the DRCF is the programmable decimating CRCF
FIR filter. The only difference between the DRCF and CRCF
filters is the coefficient bit width. The DRCF has 14-bit
coefficients, while the CRCF has 20-bit coefficients.
This filter can calculate up to 64 asymmetrical filter taps or up
to 128 symmetrical filter taps. The filter is capable of a
programmable decimation rate from 1 to 16. The flexible
coefficient offset feature allows loading multiple filters into the
coefficient RAM and changing the filters on the fly. The
decimation phase feature allows for a polyphase implementa-
tion in which multiple AD6636 channels are used to process a
single carrier.
The CRCF filter has 20-bit input and output data and 20-bit
coefficient data. The number of filter taps to calculate is
programmable and is set in the CRCF taps register. The value of
the number of taps minus one is written to this register. For
example, a value of 19 in the register corresponds to 20 filter
taps. The decimation rate is programmable using the 4-bit
CRCF decimation rate word in the CRCF control register.
Again, the value written is the decimation rate minus one.
Bypass
The CRCF filter can be used in normal operation or bypassed
using the CRCF bypass bit in the CRCF control register. When
the CRCF filter is bypassed, no scaling is applied and the output
of the filter is the same as the input to the CRCF filter.
Write the stop address for the coefficient RAM, typically
equal to ceil(NTAPS/2) – 1, in the DRCF stop address
register.
Write all coefficients to the DRCF coefficient memory
register, starting with the middle of the filter and working
towards the end of the filter. When coefficients are
numbered 0 to NTAPS – 1, the middle coefficient is given
by the coefficient number ceil(NTAPS/2). If in 8-bit
microport mode or serial port mode, write the lower byte
of the memory register first and then the higher byte. After
each write access to the DRCF coefficient memory register,
the internal RAM address is incremented starting with the
start address and ending with stop address.
Rev. A | Page 36 of 80
Scaling
The output of the CRCF filter can be scaled using the 2-bit
CRCF scaling word in the CRCF control register. Table 21
shows the valid values for the 2-bit word and the corresponding
settings. | ∑COEFF | is the sum of all coefficients (in normalized
form) used to calculate the FIR filter.
Table 21. CRCF Scaling Factor Settings
CRCF Scale Word [1:0]
00
01
10
11
Symmetry
The CRCF filter does not require symmetrical filters. However,
if the filter is symmetrical, the symmetry bit in the CRCF
control register should be set. When this bit is set, only half the
impulse response needs to be programmed into the CRCF
coefficient memory registers. For example, if the number of
filter taps is equal to 15 or 16 and the filter is symmetric, then
only eight coefficients need to be written into the coefficient
memory. Because a total of 64 taps can be written into the
memory registers, the CRCF can perform 64 asymmetrical filter
taps or 128 symmetrical filter taps.
Coefficient Offset
More than one set of filter coefficients can be loaded into the
coefficient RAM at any time (given sufficient RAM space). The
coefficient offset can be used in this case to access the two or
more different filters. By changing the coefficient offset, the
filter coefficients being accessed can be changed on the fly. This
decimal offset value is programmed in the CRCF coefficient
offset register. When this value is changed during the calcula-
tion of a particular output data sample, the sample calculation is
completed using the old coefficients, and the new coefficient
offset is brought into effect from the next data sample
calculation.
Decimation Phase
When more than one channel of the AD6636 is used to process
one carrier, polyphase implementation of the corresponding
channels’ DRCF or CRCF is possible using the decimation
phase feature. This feature can only be used under certain
conditions. The decimation phase is programmed using the
4-bit CRCF decimation phase word of the CRCF control
register.
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB