AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 66

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
<10>: ADC Port C CLK Invert Bit. Similar to Bit <11> for ADC
Port C.
<9>: ADC Port B CLK Invert Bit. Similar to Bit <11> for ADC
Port B.
<8>: ADC Port A CLK Invert Bit. Similar to Bit <11> for ADC
Port A.
<7:6>: ADC Pre-PLL Clock Divider Bits. These bits control the
PLL clock divider. The PLL clock is derived from the ADC
Port A clock.
Table 33. PLL Clock Divider Select Bits
PLL Clock Divider Bits <12:11>
00
01
10
11
<5:1>: PLL Clock Multiplier Bits. These bits control the PLL
clock multiplier. The output of the PLL clock divider is
multiplied with the binary value of these bits. The valid range
for the multiplier is from 4 to 20. A value outside this range
powers down the PLL, and the PLL clock is the same as the
ADC Port A clock.
<0>: This bit is open (write Logic 0).
Port AB, I/Q Correction Control <15:0>
<15:12>: Amplitude Loop BW. These bits set the decimation
value used in the integrator for the amplitude offset-estimation
feedback loop. A value of 0 sets a decimation of 2
of 11 sets decimation of 2
increases the decimation value by a power of 2.
<11:8>: Phase Loop BW. These bits set the decimation value
used in the integrator for the phase offset-estimation feedback
loop. A value of 0 sets a decimation of 2
decimation of 2
decimation value by a power of 2.
<7:4>: DC Loop BW. These bits set the decimation and
interpolation value used in the low-pass filters for the dc offset
estimation feedback loop. A value of 0 sets a decimation/
interpolation of 2
interpolation of 2
decimation/interpolation value by a power of 2.
<3>: Reserved.
<2>: Port AB Amplitude Correction Enable Bit. When the
amplitude correction enable bit is set, the amplitude correction
function of the I/Q correction logic for the AB port is enabled.
When this bit cleared, the amplitude correction value is given
by the value of the AB amplitude correction register. If the
Port A complex data active bit of the ADC input control register
is cleared (real input mode), this bit is a don’t care.
24
. Each increment of these bits increases the
12
24
. Each increment of these bits increases the
and a value of 11 sets decimation/
24
. Each increment of these bits
12
Divide-by Value
Divide-by-1, Bypass
Divide-by-2
Divide-by-4
Divide-by-8
and a value of 11 sets
12
and a value
Rev. A | Page 66 of 80
<1>: Port AB Phase Correction Enable Bit. When this bit is set,
the phase correction function of the I/Q correction logic for the
AB port is enabled. When this bit is cleared, the phase correction
value is given by the value of the AB phase correction register. If
the Port A complex data active bit of the ADC input control
register is cleared (real input mode), this bit is a don’t care.
<0>: Port AB DC Correction Enable Bit. When this bit is set, the
dc offset correction function of the I/Q correction block for the
AB port is enabled. When this bit is cleared, the dc offset
correction value is given by the value of the AB offset correction
registers. If the Port A complex data active bit of the ADC input
control register is cleared (real input mode), this bit is a don’t care.
Port CD, I/Q Correction Control <15:0>
<15:12>: Amplitude Loop BW. These bits set the decimation
value used in the integrator for the amplitude offset estimation
feedback loop. A value of 0 sets a decimation of 2
of 11 sets decimation of 2
increases the decimation value by a power of 2.
<11:8>: Phase Loop BW. These bits set the decimation value
used in the integrator for the phase offset estimation feedback
loop. A value of 0 sets a decimation of 2
decimation of 2
decimation value by a power of 2.
<7:4>: DC Loop BW. These bits set the decimation and
interpolation value used in the low-pass filters for the dc offset
estimation feedback loop. A value of 0 sets a decimation/
interpolation of 2
interpolation of 2
decimation/interpolation value by a power of 2.
<3>: Reserved.
<2>: Port CD Amplitude Correction Enable Bit. When this bit
is set, the amplitude correction function of the I/Q correction
logic for the AB port is enabled. When this bit is cleared, the
amplitude correction value is given by the value of the AB
amplitude correction register. If the Port A complex data active
bit of the ADC input control register is cleared (real input
mode), this bit is a don’t care.
<1>: Port CD Phase Correction Enable Bit. When this bit is set,
the phase correction function of the I/Q correction logic for the
AB port is enabled. When this bit is cleared, the phase
correction value is given by the value of the AB phase
correction register. If the Port A complex data active bit of the
ADC input control register is cleared (real input mode), this bit
is a don’t care.
24
. Each increment of these bits increases the
12
24
. Each increment of these bits increases the
and a value of 11 sets decimation/
24
. Each increment of these bits
12
and a value of 11 sets
12
and a value