AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 26

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
Table 12. Correction Control Registers
Register
I/Q Correction Control
DC Offset Correction I
DC Offset Correction Q
Amplitude Offset
Phase Offset Correction
DC Correction
All ADCs have a nominal dc offset related to them. If the ADCs
in the I and Q path have different dc offsets due to variations in
the manufacturing process, the dc correction circuit can be
used to compensate for these dc offsets. Writing Logic 1 into the
dc correction enable bit of the AB (or CD) correction control
register enables the dc correction block. Two dc estimation
blocks are used, one each for the I and Q paths. The estimated
dc value is subtracted from the I and Q paths. Therefore, the dc
signal is removed independently from the I and Q path signals.
A cascade of two low-pass decimating filters estimates the dc
offset in the feedback loop. A decimating first-order CIC filter
is followed by an interpolating second-order CIC filter. The
decimation and interpolation values of the CIC filters are the
same and are programmable between 2
The 4-bit dc loop BW word in the I/Q correction control AB (or
CD) register is used to program this decimation (interpolation)
value. When the dc loop BW is a 0, decimation is 2
the dc loop BW is 11, decimation is 2
When the dc correction circuit is enabled, the dc correction
values are estimated. The values, which are estimated independ-
ently in the I and Q paths, are subtracted independently from
their respective datapaths. These dc correction values are also
available for output continuously through the dc correction I
and dc correction Q registers. These registers contain 16-bit dc
offset values whose MSB-justified values are subtracted directly
from MSB-justified ADC inputs for the I and Q paths.
When the dc correction circuit is disabled, the value in the dc
correction register is used for continuously subtracting the dc
offset from I and Q datapaths. This method can be used to
manually set the dc offset instead of using the automatic dc
correction circuit.
Correction
Bits
15 to 12
11 to 8
7 to 4
3
2
1
0
31 to 16
15 to 0
31 to 16
15 to 0
24
.
Description
Amplitude Loop BW
Phase Loop BW
DC Loop BW
Reserved (Logic 0)
Amplitude Correction
Enable
Phase Correction Enable
DC Correction Enable
DC Offset Q
DC Offset I
Amplitude Correction
Phase Correction
12
and 2
24
in powers of 2.
12
, and when
Rev. A | Page 26 of 80
Phase Correction
When using complex ADC input, the I and Q datapaths
typically have phase offset, caused mainly by the local oscillator
and demodulator IC. The AD6636 phase-offset correction
circuit can be used to compensate for this phase offset.
When the phase correction enable bit is Logic 1, the phase error
between I and Q is estimated (ideally, the phase should be 90°).
The phase mismatch is estimated over a period of time
determined by the integrator loop bandwidth. This integrator is
implemented as a first-order CIC decimating filter, whose
decimation value can vary between 2
Phase loop BW (Bits [11:8]) of the I/Q correction control
register determine this decimation value. When phase loop BW
equals 0, the decimation value is 2
is 11, the decimation value is 2
While the phase offset correction circuit is enabled, the
tan(phase_mismatch) is estimated continuously. This value is
multiplied with Q path data and added to I path data
continuously. The estimated value is also updated in the phase
offset correction register. The tan(phase_mismatch) can be
±0.125 with a 14-bit resolution. This converts to a phase
mismatch of about ±7.125°.
When the phase offset correction circuit is disabled, the value in
the phase correction register is multiplied by the Q path data
and added to the I path data continuously. This method can be
used to manually set the phase offset instead of using the
automatic phase offset correction circuit.
Amplitude Correction
When using complex ADC input, the I and Q datapaths
typically have amplitude offset, caused mainly by the local
oscillator and the demodulator IC. The AD6636 amplitude
offset correction circuit can be used to compensate for this
amplitude offset.
When the amplitude correction enable bit is Logic 1, the
amplitude error between the I and Q datapaths is estimated.
The amplitude mismatch is estimated over a period of time
determined by the integrator loop bandwidth. This integrator is
implemented as a first-order CIC decimating filter, whose
decimation value can vary between 2
Phase loop BW (Bits [11:8]) of the I/Q correction control
register determines this decimation value. When the phase loop
BW equals 0, the decimation value is 2
BW is 11, the decimation value is 2
While the amplitude offset correction circuit is enabled, the
difference (MAG(Q) – MAG(I)) is estimated continuously. This
value is multiplied with the Q path data and added to the Q
path data continuously. The estimated value is also updated in
the phase offset correction register. The difference (MAG(Q) –
24
.
12
24
, and when phase loop BW
.
12
12
12
and 2
and 2
, and when phase loop
24
24
in powers of 2.
in powers of 2.