AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 40

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
Table 24. Definitions for Complex Control Register Selections
Complex Control Word
000
001
010
011
101
110
111
Biphase Filtering Option
The second special function that can be performed by the
second subblock of the output data router is called the biphase
filtering option. With this option, the AD6636 can be used to
process data from ADCs that run faster than the input clock
frequency by using two channels or two streams to form a
biphase filter.
For example, a 300 MHz ADC can be used with a clock rate of
150 MHz driving the ADC. The ADC data can be decimated by
2 to produce even and odd data streams of data. The even
stream can be clocked into ADC Input Port A, and the odd
stream can be clocked into ADC Input Port B. These input
ports drive separate channels or separate groups of channels.
The filters of the RCF can be designed to place a 300 MHz
sample time difference (1/300 MHz = 3.3 ns) between the even
and odd path filters.
After the channel-filter coefficients have appropriate delay, a
complex addition of the odd and even sample channels can be
performed to create a single filter. This equivalent filter looks
like a single channel with a 300 MHz input rate, even though
the clock rate of the chip runs at only 150 MHz.
A biphase filter summation is implemented by
where:
Ie × Ce, Qe × Ce are even in-phase and quadrature-phase
samples from one stream.
Io × Co and Qo × Co are odd in-phase and quadrature-phase
samples from the other stream.
Ce and Co are the even and odd coefficients, which differ by
1 high speed sample time (300 MHz in the previous example).
Output = (Ie × Ce + Io × Co) + j(Qe × Ce + Qo × Co)
Data Routing
No complex filters
Stream 0/Stream 1 combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined,
Stream 4/Stream 5 combined
Stream 0/Stream 1 Combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined
Stream 0/Stream 1 combined,
Stream 2/Stream 3 combined,
Stream 4/Stream 5 combined
Rev. A | Page 40 of 80
Comments
Stream control register controls AGC usage.
Allows Ch 0 and Ch 1 to form a complex filter.
Allows Ch 0 and Ch 1 to form a complex filter and Ch 2 and Ch 3 to
form a complex filter.
Allows Ch 0 and Ch 1 to form a complex filter, Ch 2 and Ch 3 to form a
complex filter, and Ch 4 and Ch 5 to form a complex filter.
Allows Ch 0 and Ch 1 to form a biphase filter.
Allows Ch 0 and Ch 1 to form a biphase filter, and Ch 2 and Ch 3 to
form a biphase filter.
Allows Ch 0 and Ch 1 to form a biphase filter, Ch 2 and Ch 3 to form a
biphase filter, and Ch 4 and Ch 5 to form a biphase filter.
Users can program certain streams to be summed using the
biphase filtering option. This option can be programmed using
the same 3-bit complex control word in the Parallel Output
Control 2 register. The values for the 3-bit control word and
their corresponding settings are listed in Table 24.
AUTOMATIC GAIN CONTROL
The AD6636 is equipped with six independent automatic gain
control (AGC) loops that directly follow the second data router
and immediately precede the parallel output ports. Each AGC
circuit has 96 dB of range. It is important that the decimating
filters of the AD6636 preceding the AGC reject unwanted
signals so that each AGC loop is operating on the carrier of
interest only, and carriers at other frequencies do not affect the
ranging of the loop.
The AGC compresses the 22-bit complex output from the
second data router into a programmable word size of 4 bits to
8 bits, 10 bits, 12 bits, or 16 bits. Because the small signals from
the lower bits are pushed in to higher bits by adding gain, the
clipping of the lower bits does not compromise the SNR of the
signal of interest.
The AGC maintains a constant mean power on the output
despite the level of the signal of interest, allowing operation in
environments where the dynamic range of the signal exceeds
the dynamic range of the output resolution. The output width of
the AGC is set by writing a 3-bit AGC word length word in the
AGC control register of the individual channel’s memory map.
The AGC can be bypassed, if needed, and, when bypassed, the
22-bit complex input word is still truncated to a 16-bit value
that is output through the parallel port output. The six AGCs
available on the AD6636 are programmable through the six
channel memory maps. AGCs corresponding to individual
channels can be bypassed by writing Logic 1 to AGC bypass bit
in the AGC control register.