AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 34

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
coefficient memory registers for individual channels. The input
and output data to the block are both 20 bit.
Symmetry
Though the MRCF filter does not require symmetrical filters, if
the filter is symmetrical, the symmetry bit in the MRCF control
register should be set. When this bit is set, only half of the
impulse response needs to be programmed into the MRCF
coefficient memory registers. For example, if the number of
filter taps is equal to five or six and the filter is symmetrical,
only three coefficients need to be written into the coefficient
memory. For both symmetrical and asymmetrical filters, the
number of filter taps is limited to eight.
Clock Rate
The MRCF filter runs on an internal, high speed PLL clock.
This clock rate can be as high as 200 MHz. If the half clock rate
bit in the MRCF control register is set, only half the PLL clock
rate is used (maximum of 100 MHz). This results in power
savings but can only be used if certain conditions are met.
Because this filter is nondecimating, the input and output rates
are both the same and equal to one of the following:
If HB2 is bypassed,
If HB2 is not bypassed,
If f
half of the PLL clock can be used for processing (power
savings). Otherwise, the PLL clock should be used.
Bypass
The MRCF filter can be used in normal operation or bypassed
using the MRCF bypass bit in the MRCF control register. When
the filter is bypassed, the output of the filter is the same as the
input of the filter. Bypassing the MRCF filter when it is not
required results in power savings.
Scaling
The output of the MRCF filter can be scaled by using the 2-bit
MRCF scaling word in the MRCF control register. Table 19
shows the valid values for the 2-bit word and their correspond-
ing settings.
Table 19. MRCF Scaling Factor Settings
MRCF Scale Word [1:0]
00
01
10
11
PLLCLK
f
f
MRCF
MRCF
is the PLL clock and if
= f
=
HB2
f
HB2
2
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB
f
MRCF
×
N
TAPS
≤
f
PLLCLK
2
, then
Rev. A | Page 34 of 80
DECIMATING RAM COEFFICIENT FILTER (DRCF)
Following the MRCF is the programmable DRCF FIR filter.
This filter can calculate up to 64 asymmetrical filter taps or up
to 128 symmetrical filter taps. The filter is also capable of a
programmable decimation rate of from 1 to 16. A flexible
coefficient offset feature allows loading multiple filters into the
coefficient RAM and changing the filters on the fly. The
decimation phase feature allows a polyphase implementation,
where multiple AD6636 channels are used for processing a
single carrier.
The DRCF filter has 20-bit input and output data and 14-bit
coefficient data. The number of filter taps to calculate is
programmable and is set in the DRCF taps register. The value
of the number of taps minus one is written to this register.
For example, a value of 19 in the register corresponds to
20 filter taps.
The decimation rate is programmable using the 4-bit DRCF
decimation rate word in the DRCF control register. Again, the
value written is the decimation rate minus one.
Bypass
The DRCF filter can be used in normal operation or bypassed
using the DRCF bypass bit in the DRCF control register. When
the DRCF filter is bypassed, no scaling is applied and the output
of the filter is the same as the input to the DRCF filter.
Scaling
The output of the DRCF filter can be scaled using the 2-bit
DRCF scaling word in the DRCF control register. Table 20 lists
the valid values for the 2-bit word and their corresponding
settings.
Table 20. DRCF Scaling Factor Settings
DRCF Scale Word [1:0]
00
01
10
11
Symmetry
The DRCF filter does not require symmetrical filters. However,
if the filter is symmetrical, the symmetry bit in the DRCF
control register should be set. When this bit is set, only half of
the impulse response needs to be programmed into the DRCF
coefficient memory registers. For example, if the number of
filter taps is equal to 15 or 16 and the filter is symmetrical, only
eight coefficients need to be written into the coefficient
memory. Because a total of 64 taps can be written into the
memory registers, the DRCF can perform 64 asymmetrical
filter taps or 128 symmetrical filter taps.
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB