AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 8

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
MICROPORT TIMING CHARACTERISTICS
Table 4.
Parameter
MICROPORT CLOCK TIMING REQUIREMENTS
INM MODE WRITE TIMING (MODE = 0)
INM MODE READ TIMING (MODE = 0)
MNM MODE WRITE TIMING (MODE = 1)
MNM MODE READ TIMING (MODE = 1)
1
2
3
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
C
Specification pertains to control signals: R/ W ( WR ), DS ( RD ), and CS .
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LOAD
CPUCLK
CPUCLKL
CPUCLKH
SC
HC
SAM
HAM
DRDY
ACC
SC
HC
SAM
HAM
DD
DRDY
ACC
SC
HC
SAM
HAM
DDTACK
ACC
SC
HC
SAM
HAM
DD
DDTACK
ACC
= 40 pF on all outputs, unless otherwise noted.
CPUCLK Period
CPUCLK Low Time
CPUCLK High Time
Control
Control
Address/Data to ↑CPUCLK Setup Time
Address/Data to ↑CPUCLK Hold Time
↑CPUCLK to RDY (DTACK) Delay
Write Access Time
Control
Control
Address to ↑CPUCLK Setup Time
Address to ↑CPUCLK Hold Time
↑CPUCLK to Data Delay
↑CPUCLK to RDY (DTACK) Delay
Read Access Time
Control
Control
Address/Data to ↑CPUCLK Setup Time
Address/Data to ↑CPUCLK Hold Time
↑CPUCLK to DTACK (RDY) Delay
Write Access Time
Control
Control
Address to ↑CPUCLK Setup Time
Address to ↑CPUCLK Hold Time
CPUCLK to Data Delay
↑CPUCLK to DTACK (RDY) Delay
Read Access Time
3
3
3
3
3
3
3
3
to ↑CPUCLK Hold Time
to ↑CPUCLK Setup Time
to ↑CPUCLK Hold Time
to ↑CPUCLK Setup Time
to ↑CPUCLK Hold Time
to ↑CPUCLK Setup Time
to ↑CPUCLK Hold Time
to ↑CPUCLK Setup Time
1, 2
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. A | Page 8 of 80
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
Min
10.0
1.53
1.70
0.80
0.09
0.76
0.20
3.51
3 × t
1.00
0.03
0.80
0.20
4.50
3 × t
1.00
0.00
0.00
0.57
4.10
3 × t
1.00
0.00
0.00
0.57
4.20
3 × t
CPUCLK
CPUCLK
CPUCLK
CPUCLK
0.5 × t
0.5 × t
5.0
Typ
5.0
CPUCLK
CPUCLK
Max
6.72
9 × t
6.72
9 × t
5.72
9 × t
6.03
9 × t
CPUCLK
CPUCLK
CPUCLK
CPUCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns