AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 22

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
The PLL clock multiplier is programmable and uses input clock
rates between 4 MHz and 150 MHz to give a system clock rate
(output) of as high as 200 MHz.
The output clock rate is given by
where:
CLKA is the Input Port A clock rate.
M is a 5-bit programmable multiplication factor.
N is a predivide factor.
M is a 5-bit number between 4 and 20 (both values included). N
(predivide) can be 1, 2, 4, or 8. The multiplication factor M is
programmed using a 5-bit PLL clock multiplier word in the
ADC clock control register. A value outside the valid range of 4
to 20 bypasses the PLL clock multiplier and, therefore, the PLL
clock is the same as the input clock. The predivide factor N is
programmed using a 2-bit ADC pre-PLL clock divider word in
the ADC clock control register, as listed in Table 11.
Table 11. PLL Clock Generation Predivider Control
Predivide Word [1:0]
00
01
10
11
For the best signal processing advantage, the user should
program the clock multiplier to give a system clock output as
close as possible to, but not exceeding, 200 MHz. The internal
blocks of the AD6636 that run off of the PLL clock are rated to
run at a maximum of 200 MHz. The default power-up state for
the PLL clock multiplier is the bypass state, where CLKA is
passed on as the PLL clock.
ADC GAIN CONTROL
Each ADC input port has individual, high speed, gain-control
logic circuitry. Such gain-control circuitry is useful in applica-
tions that involve large dynamic range inputs or in which gain
ranging ADCs are employed. The AD6636 gain-control logic
allows programmable upper and lower thresholds and a
programmable dwell-time counter for temporal hysteresis.
Each input port has a 3-bit output from the gain control block.
These three output pins are shared with the 3-bit exponent
input pins for each input port. The operation is controlled by
the gain control enable bit in the gain control register of the
individual input ports. Logic 1 in this bit programs the
EXP[2:0] pins as gain-control outputs, and Logic 0 configures
the pins as input exponent pins. To avoid bus contention, these
pins are set, by default, as input exponent pins.
PLL_CLK
=
CLKA
N
×
M
Divide-by Value for the Clock
Divide-by-1, bypass
Divide-by-2
Divide-by-4
Divide-by-8
Rev. A | Page 22 of 80
Function
The gain-control block features a programmable upper
threshold register and a lower threshold register. The ADC
input data is compared to both these registers. If ADC input
data is larger than the upper threshold register, then the gain
control output is decremented by 1. If ADC input data is
smaller than the lower threshold register, then the gain control
output is incremented by 1. When decrementing the gain
control output, the change is immediate. But when
incrementing the output, a dwell-time register is used to delay
the change. If the ADC input is larger than the upper threshold
register value, the gain-control output is decremented to
prevent overflow immediately.
When the ADC input is lower than the lower threshold register,
a dwell timer is loaded with the value in the programmable,
20-bit, dwell-time register. The counter decrements once every
input clock cycle, as long as the input signal remains below the
lower threshold register value. If the counter reaches 1, the gain
control output is incremented by 1. If the signal goes above the
lower threshold register value, the gain adjustment is not made,
and the normal comparison to lower and upper threshold
registers is initiated once again. Therefore, the dwell timer
provides temporal hysteresis and prevents the gain from
switching continuously.
In a typical application, if the ADC signal goes below the lower
threshold for a time greater than the dwell time, then the gain
control output is incremented by 1. Gain control bits control the
gain ranging block, which appears before the ADC in the signal
chain. With each increment of the gain control output, gain in
the gain-ranging block is increased by 6.02 dB. This increases
the dynamic range of the input signal into the ADC by 6.02 dB.
This gain is compensated for in the AD6636 by relinearizing
(see the Relinearization section). Therefore, the AD6636 can
increase the dynamic range of the ADC by 42 dB, provided that
the gain-ranging block can support it.
Relinearization
The gain in the gain-ranging block (external) is compensated
for by relinearizing, using the exponent bits, EXP[2:0], of the
input port. For this purpose, the gain control bits are connected
to the EXP[2:0] bits, providing an attenuation of 6.02 dB for
every increase in the gain control output. After the gain in the
external gain-ranging block and the attenuation in the AD6636
(using EXP bits), the signal gain is essentially unchanged. The
only change is the increase in the dynamic range of the ADC.
External gain-ranging blocks or gain-ranging ADCs have a
delay associated with changing the gain of the signal. Typically,
these delays can be up to 14 clock cycles. The gain change in the
AD6636 (via EXP[2:0]) must be synchronized with the gain
change in the gain-ranging block (external). This is allowed in
the AD6636 by providing a flexible delay, programmable 6-bit
word in the gain control register. The value in this 6-bit word