AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 43

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

The open-loop gain used in the second-order loop G(z) is given
by one of the following equations:
If Error < Error Threshold,
If Error > Error Threshold,
The open-loop transfer function for the filter, including the gain
parameter, is
If the AGC is properly configured in terms of offset in request
level, then there are no gains in the AGC loop except for the
filter gain K. Under these circumstances, a closed-loop
expression for the AGC loop is given by
The gain parameters K
through AGC loop gain 1, 2, and AGC pole location registers
from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For
example, 1000 1001 represent (137/256 = 0.535156). The error
threshold value is programmable between 0 dB and 96.3 dB in
steps of 0.024 dB. This value is programmed in the 12-bit AGC
error threshold register, using floating-point representation. It
consists of four exponent bits and eight mantissa bits. Exponent
bits are in steps of 6.02 dB and mantissa bits are in steps of
0.024 dB. For example, 0111’10001001 represents 7 × 6.02 +
137 × 0.024 = 45.428 dB.
The user defines the open-loop pole P and gain K, which also
directly impact the placement of the closed-loop poles and filter
characteristics. These closed-loop poles, P
the denominator of the previous closed-loop transfer function
and are given by
Typically, the AGC loop performance is defined in terms of its time
constant or settling time. In this case, the closed-loop poles should
be set to meet the time constants required by the AGC loop.
The relationship between the time constant and the closed-loop
poles that can be used for this purpose is
where
K = K
K = K
G
G
P
P
1
1
( )
closed
,
τ
,
z
2
P
1,
=
2
2
=
1
2
( )
exp
=
are the time constants corresponding to poles P
1
z
−
(
1
=
⎡
⎢
⎢
⎣
(
+
1
Sample
1
P
+
+
G
−
P
G
Kz
( )
z
)
K
( )
z
z
M
−
−
) (
1
1
Rate
1
±
, K
CIC
=
+
1
2
Pz
, and pole P are programmable
1
+
2
×
+
−
(
τ
2
K
P
1
,
2
−
−
⎤
⎥
⎥
⎦
1
K
−
Kz
)
2
P
−
−
)
1
z
4
−
P
1
1
, P
+
Pz
2
, are the roots of
−
2
1, 2
Rev. A | Page 43 of 80
.
The time constants can also be derived from settling times as
given by
M
time or time constant are chosen by the user. The sample rate is
the sample rate of the stream coming into the AGC. If channels
were interleaved in the output data router, then the combined
sample rate into the AGC should be considered. This rate
should be used in the calculation of poles in the previous
equation, where the sample rate is mentioned.
The loop filter output corresponds to the signal gain that is
updated by the AGC. Because all computation in the loop filter
is done in logarithmic domain (to the Base 2) of the samples,
the signal gain is generated using the exponent (power of 2) of
the loop filter output.
The gain multiplier gives the product of the signal gain with
both the I and Q data entering the AGC section. This signal
gain is applied as a coarse 4-bit scaling and then as a fine scale
8-bit multiplier. Therefore, the applied signal gain is from 0 dB
to 96.3 dB in steps of 0.024 dB. The initial signal gain is
programmable using the AGC signal gain register. This register
is again a 4 exponent + 8 mantissa bit floating-point
representation similar to the error threshold. This is taken as
the initial gain value before the AGC loop starts operating.
The products of the gain multiplier are the AGC scaled outputs
with a 19-bit representation. These are in turn used as I and Q
for calculating the power, and the AGC error and loop are
filtered to produce the signal gain for the next set of samples.
These AGC-scaled outputs can be programmed to have 4-, 5-,
6-, 7-, 8-, 10-, 12-, or 16-bit widths by using the AGC output
word length word in the AGC control register. The AGC-scaled
outputs are truncated to the required bit widths by using the
clipping circuitry, as shown in Figure 39.
Average Samples Setting
Though it is complicated to express the exact effect of the
number of averaging samples by using equations, intuitively it
has a smoothing effect on the way the AGC loop addresses a
sudden increase or a spike in the signal level. If averaging of
four samples is used, the AGC addresses a sudden increase in
signal level more slowly compared to no averaging. The same
applies to the manner in which the AGC addresses a sudden
decrease in the signal level.
Desired Clipping Level Mode
Each AGC can be configured so that the loop locks onto a
desired clipping level or a desired signal level. Desired clipping
level mode is selected by writing Logic 1 in the AGC clipping
error mode bit in the AGC control register. For signals that tend
to exceed the bounds of the peak-to-average ratio, the desired
CIC
τ
(CIC decimation is from 1 to 4,096) and either the settling
=
2%
settling
4
time
or
5%
settling
3
time
AD6636